US4912675A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single event upset hardened memory cell
Assignee: Texas Instruments Inc
•
Filing: 1988-09-07
•
Granted: 1990-03-27
•
Expires: 2008-09-07
Abstract
Abstract Single event upset hardening is provided in a static random access memory cell, including cross-coupled inverters, by the restoration of voltages at selected nodes within the cell by a pair of transistors connected to the cross-coupling between inverters.
Inventors
- 👤 Terence G. W. Blake
- 👤 Theodore W. Houston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 12:16
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/005; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/4125
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
36 words
A bi-stable logic state device comprising: a first and a second inverter; a first transistor and a first diode connected in parallel from the input of said first inverter to the output of said second inverter.
Claim 2
Dependent Claim
36 words
A bi-stable logic state device comprising: a first and a second inverter; a first transistor and a first diode connected in parallel from the input of said first inverter to the output of said second inverter.
Claim 3
Dependent Claim
53 words
A bi-stable device as recited in claim 1 wherein said first diode is connected to said first and second inverters such that the anode of said first diode is connected to the input of said first inverter and the cathode of said first diode is connected to the output of said second inverter.
Claim 4
Dependent Claim
30 words
A bi-stable logic state device as recited in claim 1 wherein said first transistor includes a body region, said body region being connected to the output of said first inverter.
Claim 5
Dependent Claim
25 words
A bi-stable logic state device as recited in claim 1 wherein said device is formed on a thin film of semiconductor material overlying an insulator.
Claim 6
Dependent Claim
37 words
A bi-stable logic state device as recited in claim 1 which further includes: a second transistor and a second diode connected in parallel from the input of said second inverter to the output of said first inverter.
Claim 7
Dependent Claim
34 words
A bi-stable logic state device as recited in claim 5 wherein said second transistor includes a body region, said body region of said second transistor being connected to the output of said second inverter.
Claim 8
Dependent Claim
19 words
A bi-stable logic state device as recited in claim 5 wherein said first and second transistors are p-channel transistors.
Claim 9
Dependent Claim
21 words
A bi-stable logic state device as recited in claim 5 wherein said first and second transistors are metal oxide semiconductor transistors.
Claim 10
Dependent Claim
19 words
A bi-stable logic state device as recited in claim 5 wherein said first and second transistors are n-channel transistors.
Claim 11
Dependent Claim
32 words
A bi-stable logic state device as recited in claim 5 wherein a first source-drain n of said first transistor includes a structure comprising a n-type semiconductor region abutting a p-type semiconductor region.
Claim 12
Dependent Claim
23 words
A bi-stable logic state device as recited in claim 10 wherein said n-type and p-type abutting regions are connected with a conductive material.
Claim 13
Dependent Claim
31 words
A bi-stable logic state device as recited in claim 5 wherein a second source/drain of said second transistor includes a structure comprising a n-type semiconductor region abutting a p-type semiconductor region.
Claim 14
Dependent Claim
34 words
A bi-stable logic state device as recited in claim 12 wherein said n-type and p-type abutting regions of said second source/drain are connected with a conductive material. drain are connected with a conductive material.
References Cited (Backward Citations)
US4725981A
Cited
US4797804A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-26 | 1993-09-25 | 1994-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-26 | 1997-09-25 | 1998-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-26 | 2001-09-25 | 2002-03-27 | $7700.00 | Window Closed / Lapsed |