US5363327A — Buried-sidewall-strap two transistor one capacito…

Claim 1

Independent Claim 170 words

A dynamic random access memory device having a plurality of memory cells comprising: a semiconductor substrate; an array of a plurality of bit lines and word lines formed on said substrate; a plurality of storage capacitors each having a pair of electrodes formed within a trench in said semiconductor substrate, the electrodes of each capacitor being isolated from the electrode of every other capacitor of said plurality of capacitors; and a pair of access field effect transistors for each storage capacitor, each transistor being formed in said substrate and having source, drain and gate regions, one of said source and drain regions of each transistor being connected to a different bit line of a bit line pair and the other of said source and drain regions of each transistor being connected to a different electrode of the respective storage capacitor, the gates of both transistors being connected to a single word line; each storage capacitor and corresponding pair of access field effect transistors forming a memory cell of said device.

Claim 2

Dependent Claim 170 words

A dynamic random access memory device having a plurality of memory cells comprising: a semiconductor substrate; an array of a plurality of bit lines and word lines formed on said substrate; a plurality of storage capacitors each having a pair of electrodes formed within a trench in said semiconductor substrate, the electrodes of each capacitor being isolated from the electrode of every other capacitor of said plurality of capacitors; and a pair of access field effect transistors for each storage capacitor, each transistor being formed in said substrate and having source, drain and gate regions, one of said source and drain regions of each transistor being connected to a different bit line of a bit line pair and the other of said source and drain regions of each transistor being connected to a different electrode of the respective storage capacitor, the gates of both transistors being connected to a single word line; each storage capacitor and corresponding pair of access field effect transistors forming a memory cell of said device.

Claim 3

Dependent Claim 95 words

The dynamic random access memory device of claim 1 wherein said bit lines and word lines are formed in a matrix of N bit lines and M word lines arranged in columns and rows on said substrate, said plurality of bit lines in said matrix including a first bit line, an Nth bit line and N-2 intermediate bit lines, each of said intermediate bit lines being connected to at least two access field effect transistors, each of said at least two access transistors being from a memory cell connected between a different bit line pair.

Claim 4

Dependent Claim 42 words

The dynamic random access memory device of claim 2 further including a plurality of sense amplifiers, each of said n bit lines including a pair of complementary acting switches for selectively connecting each bit line to one of two sense amplifier inputs.

Claim 5

Dependent Claim 28 words

The dynamic random access memory device of claim 2 wherein said bit lines, word lines, memory cells and sense amplifiers are arranged in a folded bit line architecture.

Claim 6

Dependent Claim 18 words

The random access memory device of claim 1 wherein said storage capacitor is a stacked in trench capacitor.

Claim 7

Dependent Claim 164 words

A two transistor, one capacitor, dynamic random access memory cell comprising: a semiconductor substrate of a first conductivity type; a first trench formed in said substrate, said trench having opposed sidewalls; a first insulating layer formed on said opposed sidewalls of said trench; a first conductive layer of a second conductivity type formed on said first insulating layer; a second insulating layer formed on said first conductive layer; a second conductive layer of said second conductivity type filling said trench; said first and second conductive layers and said second insulating layer forming a storage capacitor; a first field effect transistor formed in said semiconductor substrate, said transistor having source, drain and gate regions and means for connecting one of the source or drain regions to said first conductive layer; and a second field effect transistor formed in said semiconductor substrate, said transistor having source, drain and gate regions and means for connecting one of the source or drain regions to said second conductive layer.

Claim 8

Dependent Claim 164 words

A two transistor, one capacitor, dynamic random access memory cell comprising: a semiconductor substrate of a first conductivity type; a first trench formed in said substrate, said trench having opposed sidewalls; a first insulating layer formed on said opposed sidewalls of said trench; a first conductive layer of a second conductivity type formed on said first insulating layer; a second insulating layer formed on said first conductive layer; a second conductive layer of said second conductivity type filling said trench; said first and second conductive layers and said second insulating layer forming a storage capacitor; a first field effect transistor formed in said semiconductor substrate, said transistor having source, drain and gate regions and means for connecting one of the source or drain regions to said first conductive layer; and a second field effect transistor formed in said semiconductor substrate, said transistor having source, drain and gate regions and means for connecting one of the source or drain regions to said second conductive layer.

Claim 9

Dependent Claim 29 words

The memory cell of claim 6 wherein said means for connecting the source or drain regions of said first field effect transistor includes a conductive buried sidewall strap layer.

Claim 10

Dependent Claim 28 words

The memory cell of claim 7 wherein said means for connecting the source or drain regions of said second field effect transistor includes a conductive surface strap layer.

Claim 11

Dependent Claim 62 words

The memory cell of claim 7 wherein said conductive sidewall strap layer includes a second trench formed in said substrate adjacent said first trench, a third insulating layer formed on the sidewalls and bottom wall of said second trench, and a third conductive layer filling said second trench and contacting said first conductive layer through an opening in said third insulating layer.

Claim 12

Dependent Claim 56 words

The memory cell of claim 8 wherein said conductive surface strap layer includes an insulating collar surrounding an upper portion of said second conductive layer and a fourth conductive layer on the surface of said substrate contacting said upper portion and a source/drain diffusion region of said second transistor formed in the surface of said substrate.

Claim 13

Dependent Claim 27 words

The memory cell of claim 9 wherein said third conductive layer contacts a source/drain diffusion region of said first transistor formed in the surface of said substrate.

Claim 14

Dependent Claim 24 words

The dynamic random access memory device of claim 1 wherein each of said plurality of memory cells comprise the memory cell of claim 6.

Claim 15

Dependent Claim 22 words

The memory cell of claim 6 wherein said first and second conductive layers are formed on one of polysilicon or amorphous silicon.

Claim 16

Dependent Claim 22 words

The memory cell of claim 13 wherein said first insulating layer is oxide and said second insulating layer is a composite nitride/oxide.

Claim 17

Dependent Claim 18 words

The memory cell of claim 8 wherein said sidewall strap and said surface strap are formed of polysilicon.

Claim 18

Dependent Claim 71 words

A dynamic random access memory device comprising: a plurality of the memory cells of claim 6; a plurality of bit lines and word lines formed on said substrate in an array; the other of said source or drain regions of said first and second transistors being connected to a complementary pair of bit lines and the gates of both said first and second transistors being connected to a single word line.

Claim 19

Dependent Claim 95 words

The dynamic random access memory device of claim 16 wherein said bit lines and word lines are formed in a matrix of N bit lines and M word lines arranged in columns and rows on said substrate, said plurality of bit lines in said matrix including a first bit line, an Nth bit line and N-2 intermediate bit lines, each of said intermediate bit lines being connected to at least two access field effect transistors, each of said at least two access transistors being from a memory cell connected between a different bit line pair.

Claim 20

Dependent Claim 42 words

The dynamic random access memory device of claim 17 further including a plurality of sense amplifiers, each of said n bit lines including a pair of complementary acting switches for selectively connecting each bit line to one of two sense amplifier inputs.

Claim 21

Dependent Claim 28 words

The dynamic random access memory device of claim 17 wherein said bit lines, word lines, memory cells and sense amplifiers are arranged in a folded bit line architecture.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1997-11-07	1998-05-09	1998-11-08	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2001-11-07	2002-05-09	2002-11-08	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2005-11-07	2006-05-09	2006-11-08	$7700.00	Window Closed / Lapsed

Buried-sidewall-strap two transistor one capacitor trench cell

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