High density vertical trench transistor and capacitor memory cell structure and fabrication method therefor

Claim 1

A semiconductor memory cell structure of the type including a vertical access transistor self-aligned over a trench storage capacitor comprising: a semiconductor wafer including a first semiconductor type substrate and a second semiconductor type epitaxial layer disposed thereon, a relatively deep trench disposed in said epitaxial layer and substrate structure, said deep trench including a composite oxide/nitride insulation layer over the vertical and horizontal surfaces thereof to provide a storage capacitor insulator, and wherein said deep trench is filled with first semiconductor type polysilicon, a relatively shallow trench disposed in said epitaxial layer over said deep trench region, said shallow trench including an oxide insulation layer on the vertical and horizontal surface thereof, a neck structure of epitaxial polysilicon material extending from the top surface of said polysilicon filled deep trench to the bottom surface of said shallow trench disposed thereover, source regions disposed in said epitaxial layer around said neck structure between the top surface of said polysilicon filled deep trench and the bottom of said shallow trench, said total lateral width of said neck structure and said source regions being substantially smaller than the lateral width of the top surface of said deep trench, impurities disposed in said epitaxial layer on either side of said shallow trench therein to form semiconductor device drain junctions, and polysilicon material disposed in said shallow trench and over said epitaxial layer to form semiconductor device transfer gate and wordline regions respectively.