Patent US5019527A successfully refreshed from Google Patents.
EP0503199A2
Expired / Lapsed
EP
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Dynamic RAM and process for producing same
Assignee: Sharp Corp
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Filing: 1991-12-19
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Granted: —
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Expires: 2011-12-19
Abstract
Abstract A FEC-DRAM of 3 elements/2 bits type having a stacked capacitor of increased capacitance to ensure integration with an increased density. The stacked capacitor is formed as embedded in a trench, and local wiring is provided to form an electric contact on an element isolation region. When required, the stacked capacitor is made to extend onto a word line region.
Inventors
- 👤 Alberto Oscar Adan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 17:52
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/377
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
91 words
A dynamic RAM comprising: (a) a pair of MOS transistors formed side by side on a a substrate, (b) a trench formed in the substrate between impurity regions A and B adjacent to each other at one end of each of the MOS transistors, and (c) a stack capacitor comprising a first electrode layer connected to the impurity region A, a capacitor insulating layer and a second electrode layer connected to the impurity region B, the layers being formed one over another and embedded in the trench in the order mentioned.
Claim 2
Dependent Claim
32 words
A dynamic RAM as defined in claim 1 wherein the stack capacitor extends so as to partly cover a word line region serving as the gate of each of the MOS transistors.
Claim 3
Dependent Claim
122 words
A process for producing a dynamic RAM as defined in claim 1 comprising the steps of: (a) forming a trench in a substrate between impurity regions A and B adjacent to each other at one end of each of a pair of MOS transistors provided side by side on the substrate, (b) forming a local wiring strap on one of the impurity regions, B, (c) forming a first electrode layer on the other impurity region A and over the inner surface of the trench, as insulated from the local wiring strap, (d) forming a capacitor insulating layer over the first electrode layer, and (e) forming on the capacitor insulating layer a second electrode layer to be connected to the local wiring strap.
Claim 4
Dependent Claim
43 words
A process as defined in claim 3 wherein the first electrode layer, the capacitor insulating layer and the second electrode layer are each so formed as to partly cover a word line region serving as the gate of each of the MOS transistors.
References Cited (Backward Citations)
No citation records indexed.
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