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Patent US5359232A successfully refreshed from Google Patents.
US5359232A
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Clock multiplication circuit and method
Assignee: VIA Cyrix Inc
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Filing: 1992-11-13
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Granted: 1994-10-25
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Expires: 2012-11-13
Abstract
Abstract An integrated circuit, such as a microprocessor or math coprocessor, having a clock generator circuit for generating a high frequency internal clock signal based on an external input signal is disclosed. A clock generator circuit comprises circuitry for detecting an active edge of an input signal, circuitry for generating a plurality of clock edges responsive to the detection of the clock signal and circuitry for inhibiting the edge generating circuitry after generation of a predetermined number of clock edges. The factor by which the input clock signal is multiplied may be set by the circuit designer, or programmably set, without impact on the circuit design. Hence, a single circuit may be used to generate clocks of various frequencies. Further, the duty cycle of the generated clock is independent of the input clock signal.
Inventors
- 👤 John K. Eitrheim
- 👤 Richard B. Reis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:34
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H; H03; H03K; H03K5/00; H03K5/00006; H03K5/15; H03K5/15013; H03K5/15026
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
156 words
A clock multiplier circuit for generating an output clock signal with a frequency that is a multiplication of an input clock frequency, comprising: (a) a detection circuit that detects an active edge of the input clock; (b) an edge generating circuit that includes a delay line, and that provides the output clock signal defined by output clock edges; (c) the edge generating circuit being responsive to the detection of an active edge of the input clock to generate a first output clock edge corresponding to the active edge, and then to generate n more output clock edges (where n is at least two) by successively feeding back through the delay line the first output clock edge and the next n-1 output clock edges; and (d) an inhibiting circuit responsive to the generation of output clock edges to inhibit the edge generating circuitry after generation of the n output clock edges after the first output clock edge.
Claim 2
Dependent Claim
156 words
A clock multiplier circuit for generating an output clock signal with a frequency that is a multiplication of an input clock frequency, comprising: (a) a detection circuit that detects an active edge of the input clock; (b) an edge generating circuit that includes a delay line, and that provides the output clock signal defined by output clock edges; (c) the edge generating circuit being responsive to the detection of an active edge of the input clock to generate a first output clock edge corresponding to the active edge, and then to generate n more output clock edges (where n is at least two) by successively feeding back through the delay line the first output clock edge and the next n-1 output clock edges; and (d) an inhibiting circuit responsive to the generation of output clock edges to inhibit the edge generating circuitry after generation of the n output clock edges after the first output clock edge.
Claim 3
Dependent Claim
28 words
The clock multiplier of claim 1, wherein n is equal to three such that the clock multiplier output has a frequency that is 2X the input clock frequency.
Claim 4
Dependent Claim
23 words
The clock multiplier of claim 1 wherein said inhibiting circuitry is reset responsive to detection of an active edge of the input clock.
Claim 5
Dependent Claim
70 words
The clock multiplier of claim 1 wherein said edge generating circuitry comprises: delay circuitry that receives a signal and outputs said same signal after a predefined delay; edge detection circuitry coupled to said delay circuitry that detects a predetermined transition of the output of said delay circuitry and generates a detection signal in response thereto; and transition circuitry that generates a clock edge transition responsive to said edge detection circuitry.
Claim 6
Dependent Claim
16 words
The clock multiplier of claim 4 wherein said transition circuitry comprises a SR flip flop circuit.
Claim 7
Dependent Claim
52 words
The clock multiplier of claim 1 wherein said inhibiting circuitry comprises: counting circuitry for counting generated output clock edges; and comparator circuitry for comparing the output of said counting circuitry with a predetermined number and for generating an inhibiting signal indicating whether the output of said counting circuitry equals said predetermined number.
Claim 8
Independent Claim
113 words
A method of generating a clock signal with a frequency that is a multiplication of an input clock frequency, comprising the steps of: (a) detecting an active edge of the input clock; (b) responsive to the detection of an active edge of the input clock, generating a first output clock edge corresponding to the active edge, and then generating n more output clock edges (where n is at least two) by successively feeding back through a delay line the first output clock edge and the next n-1 output clock edges; and (c) inhibiting the generation of output clock edges after generation of the n output clock edges after the first output clock edge.
Claim 9
Independent Claim
113 words
A method of generating a clock signal with a frequency that is a multiplication of an input clock frequency, comprising the steps of: (a) detecting an active edge of the input clock; (b) responsive to the detection of an active edge of the input clock, generating a first output clock edge corresponding to the active edge, and then generating n more output clock edges (where n is at least two) by successively feeding back through a delay line the first output clock edge and the next n-1 output clock edges; and (c) inhibiting the generation of output clock edges after generation of the n output clock edges after the first output clock edge.
Claim 10
Dependent Claim
27 words
The method of claim 7, wherein n is equal to three such that the generated clock signal has a frequency that is 2X the input clock frequency.
Claim 11
Dependent Claim
51 words
The method of claim 7 wherein said generating step comprises the step of: receiving a signal and outputting said same signal after a predefined delay; detecting a predetermined transition of the delayed signal and generating a detection signal in response thereto; and generating a clock transition responsive to said detection signal.
Claim 12
Dependent Claim
47 words
The method of claim 7 wherein said inhibiting step comprises the steps of: counting clock edges the generated output clock signal; comparing the number of counted edges with a predetermined number and generating an inhibiting signal indicating the output of said counting circuitry equals said predetermined number.
Claim 13
Dependent Claim
29 words
The method of claim 10 and further comprising the step of resetting the count of clock edges responsive to detection of an active edge of said input clock signal.
Claim 14
Dependent Claim
145 words
A clock multiplier circuit for generating an output clock signal with a frequency that is a multiplication of an input clock frequency, comprising: (a) detection means for detecting an active edge of the input clock; (b) edge generating means, including a delay line, responsive to the detection of an active edge of the input clock for generating a first output clock edge corresponding to the active edge, and then generating n more output clock edges (where n is at least two) by successively feeding back through the delay line the first output clock edge and the next n-1 output clock edges, thereby providing the output clock signal defined by the output clock edges; and (c) inhibiting means responsive to the generation of output clock edges for inhibiting the edge generating circuitry after generation of the n output clock edges after the first output clock edge.
Claim 15
Dependent Claim
145 words
A clock multiplier circuit for generating an output clock signal with a frequency that is a multiplication of an input clock frequency, comprising: (a) detection means for detecting an active edge of the input clock; (b) edge generating means, including a delay line, responsive to the detection of an active edge of the input clock for generating a first output clock edge corresponding to the active edge, and then generating n more output clock edges (where n is at least two) by successively feeding back through the delay line the first output clock edge and the next n-1 output clock edges, thereby providing the output clock signal defined by the output clock edges; and (c) inhibiting means responsive to the generation of output clock edges for inhibiting the edge generating circuitry after generation of the n output clock edges after the first output clock edge.
Claim 16
Dependent Claim
28 words
The clock multiplier of claim 12, wherein n is equal to three such that the clock multiplier output has a frequency that is 2X the input clock frequency.
Claim 17
Dependent Claim
60 words
The clock multiplier of claim 12 wherein said edge generating means comprises: a logic gate for outputting the generated clock signal; delay circuitry coupled to the output of said logic gate; and edge detectors coupled to said delay circuitry and said logic gate for controlling the output state of said logic gate responsive to the output of said edge detectors.
Claim 18
Dependent Claim
14 words
The clock circuitry of claim 14 wherein said logic gate comprises an SR flip-flop.
Claim 19
Dependent Claim
59 words
The clock multiplier of claim 14 wherein said inhibiting circuitry comprises: counting circuitry for counting transitions of said generated output clock signal; a comparator coupled to said counting circuit; and logic circuitry coupled for said comparator to electrically decoupling said edge detectors from said logic gate after a predetermined number of counted transitions of said generated output clock signal.
Claim 20
Dependent Claim
23 words
The clock circuitry of claim 16 wherein said counting circuitry is reset upon detection of a next active edge of the input clock.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-10-24 | 1998-04-25 | 1998-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-24 | 2002-04-25 | 2002-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-24 | 2006-04-25 | 2006-10-25 | $7700.00 | Window Closed / Lapsed |