Address transition detector circuit

Claim 2

A semiconductor integrated circuit including a detection circuit for detecting a change of at least one of a first and a second digital input signal on a first and a second input terminal, respectively, the detection circuit delivering an output pulse signal having a predetermined duration in response to said change, the detection circuit comprising: a first resettable delay circuit having an input terminal for receiving said first input signal, a reset terminal coupled to said input terminal and an output terminal for delivering a first output signal; a second resettable delay circuit having an input terminal for receiving said second input signal, a reset terminal coupled to said input terminal and an output terminal for delivering a second output signal; and a gate circuit having input terminals and an output terminal for delivering said output pulse signal on said output terminal; said first and second input terminals and said output terminals of the first and second delay circuits being connected directly to respective input terminals of said gate circuit.

Claim 3

A semiconductor integrated circuit according to claim 1, characterized in that at least one of the first and the second delay circuits comprises at least one inverter and one NAND-gate.

Claim 4

A semiconductor integrated circuit according to claim 1, characterized in that said gate circuit is an exclusive-OR gate.

Claim 5

A semiconductor integrated circuit according to claim 1, characterized in that said gate circuit is a non-exclusive-OR gate.

Claim 6

A semiconductor integrated circuit according to claim 4, characterized in that said non-exclusive-OR gate comprises four PMOS-transistors and four NMOS-transistors, an output of the non-exclusive-OR gate being connected to a first power supply via a first and a second PMOS-transistor which are connected in series, the output of the non-exclusive-OR gate being connected to the first power supply via a third and a fourth PMOS-transistor which are connected in series, the output of the non-exclusive-OR gate being connected to a second power supply via a first and a second NMOS-transistor which are connected in series, and the output of the non-exclusive-OR gate being connected to the second power supply via a third and a fourth NMOS-transistor which are connected in series, the gate of the first and third PMOS-transistors receiving the second and first output signal, respectively, the gate of the second and fourth PMOS-transistors receiving the first and second input signal, respectively, the gate of the first and third NMOS-transistors receiving the first and second output signal, respectively, and the gate of the second and fourth NMOS-transistors receiving the first and second input signal, respectively.

Claim 7

A semiconductor integrated circuit according to claim 5, characterized in that said non-exclusive-OR gate comprises a fifth and a sixth PMOS-transistor which are connected in parallel with the second and fourth PMOS-transistors, respectively, the gate of the fifth and sixth PMOS-transistors receiving the first and the second output signal, respectively.

Claim 8

A semiconductor integrated circuit according to claim 5, characterized in that said non-exclusive-OR gate comprises a fifth and a sixth NMOS-transistors which are connected in parallel with the first and third NMOS-transistors respectively, the gate of the fifth and sixth NMOS-transistors receiving the second and first input signal, respectively.