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Patent US5357146A successfully refreshed from Google Patents.
US5357146A
Expired / Lapsed
US
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Glitch-free clock multiplexer
Assignee: Nokia Bell Labs
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Filing: 1992-12-31
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Granted: 1994-10-18
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Expires: 2012-12-31
Abstract
Abstract A multiplexer for selecting one of at least two input signals as the output on sensing the change in the state of a select input waits for the clock signal of the active first clock to transition to a predetermined state, disconnects the active first clock from the output of the multiplexer and maintains the output of the multiplexer in the predetermined state while waiting for the clock signal of a second clock to transition to the predetermined state. The second clock is connected as the multiplexer output while the clock signal of the second clock is in the predetermined state. In a preferred embodiment, the predetermined state is a low logic level.
Inventors
- 👤 Martin E. Heimann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:50
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/08; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
312 words
An integrated circuit including a multiplexer for selecting one of at least two clock signals as the output signal, comprising: a first shift register for receiving a select input, the first shift register clocked by a first clock signal, said first shift register providing a first shift register output and an inverted first shift register output; a second shift register for receiving the select input, the second shift register clocked by a second clock signal, said second shift register providing a second shift register output; a third shift register for receiving as an input the first shift register output, said third shift register clocked by the second clock signal, said third shift register providing a third shift register output; a fourth shift register for receiving as an input the second shift register output, said fourth shift register clocked by the first clock signal, said fourth shift register providing an inverted fourth shift register output; first gate means for receiving as inputs the second clock signal, the third shift register output, and the second shift register output, the first gate means providing a first gate means output that is low when all inputs are in a high state, and is high when at least one input is in a low state; second gate means for receiving as inputs the first clock signal, the inverted fourth shift register output, and the first shift register output, the second gate means providing a second gate means output that is low when all inputs are in a high state, and is high when at least one input is in a low state; and third gate means for receiving as inputs the first and second gate means outputs, the third gate means providing an output that is low when both inputs are in a high state and high when at least one input is in a low state.
Claim 2
Dependent Claim
312 words
An integrated circuit including a multiplexer for selecting one of at least two clock signals as the output signal, comprising: a first shift register for receiving a select input, the first shift register clocked by a first clock signal, said first shift register providing a first shift register output and an inverted first shift register output; a second shift register for receiving the select input, the second shift register clocked by a second clock signal, said second shift register providing a second shift register output; a third shift register for receiving as an input the first shift register output, said third shift register clocked by the second clock signal, said third shift register providing a third shift register output; a fourth shift register for receiving as an input the second shift register output, said fourth shift register clocked by the first clock signal, said fourth shift register providing an inverted fourth shift register output; first gate means for receiving as inputs the second clock signal, the third shift register output, and the second shift register output, the first gate means providing a first gate means output that is low when all inputs are in a high state, and is high when at least one input is in a low state; second gate means for receiving as inputs the first clock signal, the inverted fourth shift register output, and the first shift register output, the second gate means providing a second gate means output that is low when all inputs are in a high state, and is high when at least one input is in a low state; and third gate means for receiving as inputs the first and second gate means outputs, the third gate means providing an output that is low when both inputs are in a high state and high when at least one input is in a low state.
Claim 3
Dependent Claim
34 words
An integrated circuit as recited in claim 1, wherein each of the shift registers further comprises a reset input such that on power-up each shift register can be cleared to provide a known output.
Claim 4
Dependent Claim
25 words
An integrated circuit as recited in claim 1, wherein one of the first and second clock signals is recovered from data read from a disk.
Claim 5
Independent Claim
358 words
A system including a multiplexer for selecting one of at least two clock signals as the output signal, comprising: a magnetic medium; a read-write channel to read data from or write data to the magnetic medium, the read-write channel responsive to a first clock signal when writing data to the magnetic medium, the read-write channel recovering a second clock signal from data read from the magnetic medium; a first shift register for receiving a select input, the first shift register clocked by the first clock signal, said first shift register providing a first shift register output and an inverted first shift register output; a second shift register for receiving the select input, the second shift register clocked by the second clock signal, said shift register providing a second shift register output; a third shift register for receiving as an input the first shift register output, said third shift register clocked by the second clock signal, said third shift register providing a third shift register output; a fourth shift register for receiving as an input the second shift register output, said fourth shift register clocked by the first clock signal, said fourth shift register providing an inverted fourth shift register output; first gate means for receiving as inputs the second clock signal, the third shift register output, and the second shift register output, the first gate means providing a first gate means output that is low when all inputs are in a high state, and is high when at least one input is in a low state; second gate means for receiving as inputs the first clock signal, the inverted fourth shift register output, and the first shift register output, the second gate means providing a second gate means output that is low when all inputs are in a high state, and is high when at least one input is in a low state; and third gate means for receiving as inputs the first and second gate means outputs, the third gate means providing an output that is low when both inputs are in a high state and high when at least one input is in a low state.
Claim 6
Independent Claim
358 words
A system including a multiplexer for selecting one of at least two clock signals as the output signal, comprising: a magnetic medium; a read-write channel to read data from or write data to the magnetic medium, the read-write channel responsive to a first clock signal when writing data to the magnetic medium, the read-write channel recovering a second clock signal from data read from the magnetic medium; a first shift register for receiving a select input, the first shift register clocked by the first clock signal, said first shift register providing a first shift register output and an inverted first shift register output; a second shift register for receiving the select input, the second shift register clocked by the second clock signal, said shift register providing a second shift register output; a third shift register for receiving as an input the first shift register output, said third shift register clocked by the second clock signal, said third shift register providing a third shift register output; a fourth shift register for receiving as an input the second shift register output, said fourth shift register clocked by the first clock signal, said fourth shift register providing an inverted fourth shift register output; first gate means for receiving as inputs the second clock signal, the third shift register output, and the second shift register output, the first gate means providing a first gate means output that is low when all inputs are in a high state, and is high when at least one input is in a low state; second gate means for receiving as inputs the first clock signal, the inverted fourth shift register output, and the first shift register output, the second gate means providing a second gate means output that is low when all inputs are in a high state, and is high when at least one input is in a low state; and third gate means for receiving as inputs the first and second gate means outputs, the third gate means providing an output that is low when both inputs are in a high state and high when at least one input is in a low state.
Claim 7
Dependent Claim
33 words
A system as recited in claim 4, wherein each of the shift registers further comprises a reset input such that on power-up each shift register can be cleared to provide a known output.
References Cited (Backward Citations)
US4229699A
Cited
US4314164A
Cited
US4593390A
Cited
US4694196A
Cited
US4644568A
Cited
US4970405A
Cited
US4853653A
Cited
US4998901A
Cited
US5099141A
Cited
US5122677A
Cited
US5155380A
Cited
US5254888A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-17 | 1998-04-18 | 1998-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-17 | 2002-04-18 | 2002-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-17 | 2006-04-18 | 2006-10-18 | $7700.00 | Window Closed / Lapsed |