US5122677A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Instantaneous breakless clock switching apparatus
Assignee: Fujitsu Ltd
•
Filing: 1991-09-03
•
Granted: 1992-06-16
•
Expires: 2011-09-03
Abstract
Abstract A clock switching apparatus includes a first phase synchronizing part for receiving n (n is an integer) input clock signals and for generating n first clock signals respectively related to the n input clock signals. Each of the n first clock signals has a frequency higher than that of a corresponding one of the n input clock signals. A selector selects one of the n first clock signals. A frequency divider generates a second clock signal obtained by frequency-dividing the one of the n first clock signals selected by the selector. A second phase synchronizing part generates an output clock signal synchronized with the second clock signal.
Inventors
- 👤 Sakutaro Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 01:25
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0635; H04J3/0685; H04J3/0688; H03; H03L; H03L7/00; H03L7/06; H03L7/07
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
130 words
A clock switching apparatus comprising: first phase synchronizing means for receiving n (n is an integer) input clock signals and for generating n first clock signals respectively related to said n input clock signals, each of said n first clock signals having a frequency higher than that of a corresponding one of said n input clock signals; selector means, coupled to said first phase synchronizing means, for selecting one of the n first clock signals; first frequency dividing means, coupled to said selector means, for generating a second clock signal obtained by frequency-dividing said one of the n first clock signals selected by said selector means; and second phase synchronizing means, coupled to said first frequency dividing means, for generating an output clock signal synchronized with said second clock signal.
Claim 2
Dependent Claim
130 words
A clock switching apparatus comprising: first phase synchronizing means for receiving n (n is an integer) input clock signals and for generating n first clock signals respectively related to said n input clock signals, each of said n first clock signals having a frequency higher than that of a corresponding one of said n input clock signals; selector means, coupled to said first phase synchronizing means, for selecting one of the n first clock signals; first frequency dividing means, coupled to said selector means, for generating a second clock signal obtained by frequency-dividing said one of the n first clock signals selected by said selector means; and second phase synchronizing means, coupled to said first frequency dividing means, for generating an output clock signal synchronized with said second clock signal.
Claim 3
Dependent Claim
104 words
A clock switching apparatus as claimed in claim 1, wherein said first phase synchronizing means comprises n PLL circuits respectively related to said n input clock signals, and wherein each of said n PLL circuits comprises: a generator generating one of said n first clock signals; a frequency divider generating a frequency-divided clock signal by frequency-dividing said one of the n first clock signals generated by said generator; and a phase comparator comparing the phase of one of the n input clock signals with the phase of said frequency-divided clock signal and for controlling said generator so that a phase difference therebetween is zero.
Claim 4
Dependent Claim
77 words
A clock switching apparatus as claimed in claim 1, wherein said second phase synchronizing means comprises: a generator generating said output clock signal; a frequency divider generating a frequency-divided clock signal by frequency-dividing said output clock signal; and a phase comparator comparing the phase of said frequency-divided clock signal with the phase of said second clock signal generated by said first frequency dividing means and for controlling said generator so that a phase difference therebetween is zero.
Claim 5
Dependent Claim
43 words
A clock switching apparatus as claimed in claim 1, further comprising signal break detecting means for detecting a signal break of each of said n input clock signals and for controlling said selector on the basis of results of detecting the signal break.
Claim 6
Dependent Claim
63 words
A clock switching apparatus as claimed in claim 1, further comprising signal break detecting means for detecting a signal break of each of said n input clock signals and for outputting detection signals showing results of detecting the signal break to said selector means, wherein said selector means comprises means for indicating which one of said n first clock signals should be selected.
Claim 7
Dependent Claim
43 words
A clock switching apparatus as claimed in claim 1, further comprising second frequency dividing means for frequency-dividing a master clock signal supplied from an external device and for generating at least one of said n input clock signals from said master clock signal.
Claim 8
Dependent Claim
31 words
A clock switching apparatus as claimed in claim 1, further comprising internal clock signal generating means for generating an internal clock signal which is one of said n input clock signals.
Claim 9
Dependent Claim
43 words
A clock switching apparatus as claimed in claim 1, further comprising second frequency dividing means for frequency-dividing an extracted clock signal supplied from an external device and for generating at least one of said n input clock signals from said extracted clock signal.
Claim 10
Dependent Claim
30 words
A clock switching apparatus as claimed in claim 2, wherein said frequency-divided clock signal has a frequency equal to that of a corresponding one of said n input clock signals.
Claim 11
Dependent Claim
25 words
A clock switching apparatus as claimed in claim 3, wherein said frequency-divided clock signal has a frequency equal to that of said second clock signal.
References Cited (Backward Citations)
US4860283A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-16 | 1995-12-16 | 1996-06-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-16 | 1999-12-16 | 2000-06-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-16 | 2003-12-16 | 2004-06-16 | $7700.00 | Window Closed / Lapsed |