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US5356828A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming micro-trench isolation regions in the fabrication of semiconductor devices

Assignee: Hewlett Packard Development Co LP
•
Filing: 1993-07-01
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Granted: 1994-10-18
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Expires: 2013-07-01
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Abstract

Abstract A method of forming micro-trench isolation regions with a separation of 0.20 mu m to 0.35 mu m in the fabrication of semiconductor devices involves forming an silicon dioxide layer on select locations of a semiconductor substrate and depositing a polysilicon layer onto the silicon dioxide layer. A layer of photoresist is then deposited over select areas of the polysilicon layer and patterned to form micro-trench isolation regions of widths between about 0.2 mu m to about 0.5 mu m and aspect ratio of between about 2:1 to about 7:1. Thereafter, the isolation regions are etched for a time and pressure sufficient to form micro-trenches in the substrate surface. The micro-trenches will generally have a width ranging from about 1000 ANGSTROM to about 3500 ANGSTROM and depth ranging from about 500 ANGSTROM to about 5000 ANGSTROM . The layer of photoresist is then removed to expose the polysilicon layer and a channel stop implant is deposited and aligned with the micro-trenches. A thermal silicon dioxide layer is formed in the micro-trenches and an undoped silicon dioxide layer is deposited onto the polysilicon layer to fill the micro-trenches. A planar silicon dioxide layer is then deposited onto the undoped silicon dioxide layer and the undoped and planar silicon dioxide layers are then etched back to expose the polysilicon layer. After etchback, the polysilicon layer is stripped to provide the micro-trench isolation regions.

Inventors

  • 👤 Stephen W. Swan
  • 👤 Ellen G. Piccioli

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 14:59
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0145; H10W10/10; H10W10/17; Y; Y10; Y10S; Y10S148/00; Y10S148/05

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 148 words
A method of forming micro-trench isolation regions in the fabrication of semiconductor devices comprising: forming a first silicon dioxide layer on a semiconductor substrate surface; depositing a hard film layer on the first silicon dioxide layer; depositing a layer of photoresist over the hard film layer and patterning the photoresist to provide open regions having widths between 0.2 μm to 0.5 μm and an aspect ratio of photoresist and hard film layer thickness to open region width of between 2:1 to 7:1; etching the exposed hard film by a plasma etch process to form micro-trenches in the substrate surface having widths between 1000 Å to 3500 Å; removing the layer of photoresist to expose the hard film layer; implanting an n- or p-channel-stop inplant into the substrate and aligned with the micro-trenches; and forming and planarizing a second silicon dioxide layer in the micro-trenches of the substrate surface.
Claim 2
Independent Claim 148 words
A method of forming micro-trench isolation regions in the fabrication of semiconductor devices comprising: forming a first silicon dioxide layer on a semiconductor substrate surface; depositing a hard film layer on the first silicon dioxide layer; depositing a layer of photoresist over the hard film layer and patterning the photoresist to provide open regions having widths between 0.2 μm to 0.5 μm and an aspect ratio of photoresist and hard film layer thickness to open region width of between 2:1 to 7:1; etching the exposed hard film by a plasma etch process to form micro-trenches in the substrate surface having widths between 1000 Å to 3500 Å; removing the layer of photoresist to expose the hard film layer; implanting an n- or p-channel-stop inplant into the substrate and aligned with the micro-trenches; and forming and planarizing a second silicon dioxide layer in the micro-trenches of the substrate surface.
Claim 3
Dependent Claim 14 words
The method of claim 1 wherein the semiconductor substrate is doped or undoped silicon.
Claim 4
Dependent Claim 21 words
The method of claim 1 wherein the first silicon dioxide layer ranges from 60 Å to 120 Å silicon dioxide thick.
Claim 5
Dependent Claim 13 words
The method of claim 1 wherein the hard film is undoped silicon nitride.
Claim 6
Dependent Claim 12 words
The method of claim 1 wherein the hard film is doped polysilicon.
Claim 7
Dependent Claim 12 words
The method of claim 1 wherein the hard film is doped polysilicon.
Claim 8
Dependent Claim 16 words
The method of claim 1 wherein the photoresist is between 0.5 μm to 2.0 μm thick.
Claim 9
Dependent Claim 25 words
The method of claim 1 wherein the etching of the exposed hard film is performed at a pressure of between 200 mT and 500 mT.
Claim 10
Dependent Claim 26 words
The method of claim 1 wherein the etching of the exposed hard film is accomplished with an etchant having a polysilicon:oxide selectivity of greater than 30:1.
Claim 11
Dependent Claim 27 words
The method of claim 1 wherein the micro-trench formed in the substrate layer is 1000 Å to 3500 Å wide and 500 Å to 5000 Å deep.
Claim 12
Dependent Claim 80 words
The method of claim 1 wherein the second silicon dioxide layer is formed by the steps comprising: forming a thermal silicon dioxide layer in the micro-trenches; depositing a second silicon dioxide layer onto the hard film layer to fill the micro-trenches; depositing a planar silicon dioxide layer onto the second silicon dioxide layer; etching the second and planar silicon dioxide layers to expose the hard film layer; and stripping the hard film layer to provide a planarized micro-trench isolation region.
Claim 13
Dependent Claim 23 words
The method of claim 11 wherein the thermal silicon dioxide layer formed in the micro-trenches is between 200 Å and 2400 Å thick.
Claim 14
Dependent Claim 16 words
The method of claim 11 wherein the planar silicon dioxide layer is a doped silicon dioxide.
Claim 15
Dependent Claim 26 words
The method of claim 11 wherein the hard film layer is stripped in a plasma process with an etchant having a polysilicon:oxide selectivity greater than 40:1.

References Cited (Backward Citations)

US4104086A Cited
US4419813A Cited
US4506434A Cited
US4465532A Cited
JPS59135743A Cited
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US5118384A Cited
US5175122A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-10-17 1998-04-18 1998-10-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-10-17 2002-04-18 2002-10-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-10-17 2006-04-18 2006-10-18 $7700.00 Window Closed / Lapsed

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