US4465532A
Expired / Lapsed
US
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Method for forming an isolation region for electrically isolating elements
Assignee: Fujitsu Ltd
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Filing: 1983-11-07
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Granted: 1984-08-14
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Expires: 2003-11-07
Abstract
Abstract A method for forming an isolation region having a submicron width thereof in a semiconductor substrate includes the steps of forming a metal or a metal silicide layer on the semiconductor substrate then forming a resist layer on the metal or metal silicide layer and patterning the resist layer. The method further includes selectively etching the metal or metal silicide layer and the semiconductor substrate by the reactive ion etching process using a mixture of chlorine-containing gas and oxygen gas to form a groove in the surface portion of the semiconductor substrate located around the edge of the resist layer and forming an insulating layer in the groove.
Inventors
- 👤 Tetsu Fukano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:38
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/61; H10P50/00; H10P50/69; H10P50/691; H10P76/00; H10P76/40; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/014; H10W10/041; H10W10/10; H10W10/13; H10W10/17; H10W10/40
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
95 words
A method for forming an isolation region for electrically isolating elements in a semiconductor substrate, comprising the steps of: (a) forming a metal layer on the semiconductor substrate; (b) forming a resist layer on the metal layer; (c) patterning the resist layer; (d) selectively etching the metal and the semiconductor substrate by a reactive ion etching process using a mixture of chlorine-containing gas and oxygen gas to form a groove in the surface portion of the semiconductor substrate located around the periphery of the resist layer; and (e) forming an insulating layer in the groove.
Claim 2
Independent Claim
95 words
A method for forming an isolation region for electrically isolating elements in a semiconductor substrate, comprising the steps of: (a) forming a metal layer on the semiconductor substrate; (b) forming a resist layer on the metal layer; (c) patterning the resist layer; (d) selectively etching the metal and the semiconductor substrate by a reactive ion etching process using a mixture of chlorine-containing gas and oxygen gas to form a groove in the surface portion of the semiconductor substrate located around the periphery of the resist layer; and (e) forming an insulating layer in the groove.
Claim 3
Dependent Claim
26 words
A method according to claim 1, wherein said step (a) comprises selecting the metal selected from the group consisting of molybdenum, tungsten, titanium, platinum and tantalum.
Claim 4
Dependent Claim
31 words
A method according to claim 1, wherein said step (a) comprises selecting the metal silicide from the group consisting of molybdenum silicide, tungsten silicide, titanium silicide, platinum silicide and tantalum silicide.
Claim 5
Dependent Claim
32 words
A method according to claim 1, wherein said step (d) comprises selectively etching the metal layer using a chlorine-containing gas selected from the group of carbon tetrachloride, silicon tetrachloride and boron trichloride.
Claim 6
Dependent Claim
69 words
A method according to claim 4, wherein said step (d) comprises reactive ion etching by using a mixed gas of oxygen and carbon tetrachloride at a power density of 0.14 to 0.35 W/cm 2 and in a vacuum having a pressure of 1 to 10 Pa, for 3 to 30 minutes, the volume percentage of oxygen in the mixed gas of oxygen and carbon tetrachloride being 60% to 70%.
Claim 7
Dependent Claim
37 words
A method according to claim 1, wherein said step (e) comprises forming the insulating layer in the groove by a thermal oxidation process at a temperature of 800° C. to 1100° C. under a wet oxidation atmosphere.
Claim 8
Dependent Claim
24 words
A method according to claim 1, wherein said step (e) comprises forming the insulating layer in the groove by a chemical vapor deposition process.
Claim 9
Dependent Claim
68 words
A method according to claim 1, wherein said step (e) of forming the insulating layer in the groove comprises the substeps of: (i) oxidizing the whole inner wall of the groove by a first thermal oxidation process; (ii) burying the groove in polycrystalline silicon by a chemical vapor deposition process; and (iii) oxidizing the exposed surface of polycrystalline silicon in the groove by a second thermal oxidation process.
Claim 10
Independent Claim
124 words
A method for forming an isolation region for electrically isolating elements in a semiconductor substrate having a surface portion, comprising the steps of: (a) forming a first insulating layer; (b) forming a metal layer on the first insulating layer; (c) forming a resist layer on the metal layer; (d) patterning the resist layer; (e) selectively etching the metal layer by a reactive ion etching process using a mixture of chlorine-containing gas and oxygen gas; (f) etching the first insulating layer using the metal layer as a masking film; (g) etching the semiconductor substrate using the etched insulating layer as a masking film to form a groove in the surface portion of the semiconductor substrate; and (h) forming a second insulating layer in the groove.
Claim 11
Independent Claim
124 words
A method for forming an isolation region for electrically isolating elements in a semiconductor substrate having a surface portion, comprising the steps of: (a) forming a first insulating layer; (b) forming a metal layer on the first insulating layer; (c) forming a resist layer on the metal layer; (d) patterning the resist layer; (e) selectively etching the metal layer by a reactive ion etching process using a mixture of chlorine-containing gas and oxygen gas; (f) etching the first insulating layer using the metal layer as a masking film; (g) etching the semiconductor substrate using the etched insulating layer as a masking film to form a groove in the surface portion of the semiconductor substrate; and (h) forming a second insulating layer in the groove.
Claim 12
Dependent Claim
26 words
A method according to claim 9, wherein said step (a) comprises selecting the first insulating layer from the group consisting of silicon nitride and silicon dioxide.
Claim 13
Dependent Claim
25 words
A method according to claim 9, wherein said step (b) comprises selecting the metal from the group consisting of molybdenum, tungsten, titanium, platinum, and tantalum.
Claim 14
Dependent Claim
31 words
A method according to claim 1, wherein said step (b) comprises selecting the metal silicide from the group consisting of molybdenum silicide, tungsten silicide, titanium silicide, platinum silicide, and tantalum silicide.
Claim 15
Dependent Claim
27 words
A method according to claim 9, wherein said step (e) comprises selecting the chlorine-containing gas from the group consisting of carbon tetrachloride, silicon tetrachloride and boron trichloride.
Claim 16
Dependent Claim
68 words
A method according to claim 9, wherein said step (e) comprises reactive ion etching using a mixed gas of oxygen and carbon tetrachloride at a power density of 0.14 to 0.35 W/cm 2 and in a vacuum having a pressure of 1 to 10 Pa, for 1 to 9 minutes, the volume percentage of oxygen in the mixed gas of oxygen and carbon tetrachloride being 60% to 70%.
Claim 17
Dependent Claim
55 words
A method according to claim 9, wherein said step (f) comprises etching the first insulating layer by a reactive ion etching process using an etching gas of trifluoromethane at a power density of 0.06 to 0.8 W/cm 2 and in a vacuum having a pressure of 0.9 to 13 Pa, for 3 to 30 minutes.
Claim 18
Dependent Claim
74 words
A method according to claim 9, wherein said step (g) comprises etching the semiconductor substrate by a reactive ion etching process using a mixed gas of oxygen and carbon tetrachloride at a power of 0.14 to 0.35 W/cm 2 and in a vacuum having a pressure of 1 to 10 Pa, for 3 to 30 minutes, the volume percentage of oxygen in the mixed gas of oxygen and carbon tetrachloride being less than 50%.
Claim 19
Dependent Claim
34 words
A method according to claim 9, wherein said step (f) comprises forming the insulating layer by a thermal oxidation process at a temperature of 800° C. to 1100° C. under a wet oxidation atmosphere.
Claim 20
Dependent Claim
25 words
A method according to claim 9, wherein said step (h) comprises forming the second insulating layer in the groove by a chemical vapor deposition process.
Claim 21
Dependent Claim
57 words
A method according to claim 9, wherein said step (f) comprises the substeps of: (i) oxidizing the whole inner wall of the groove by a first thermal oxidation process: (ii) burying the groove in polycrystalline silicon by the chemical vapor deposition process; and (iii) oxidizing the exposed surface of the groove by a second thermal oxidation process.
Claim 22
Independent Claim
98 words
A method for forming an isolation region for electrically isolating elements in a semiconductor substrate, comprising the steps of: (a) forming a metal silicide layer on the semiconductor substrate; (b) forming a resist layer on the metal silicide layer; (c) patterning the resist layer; (d) selectively etching the metal silicide layer and the semiconductor substrate by a reactive ion etching process using a mixture of chlorine-containing gas and oxygen gas to form a groove in the surface portion of the semiconductor substrate surrounding the periphery of the resist layer; and (e) forming an insulating layer in the groove.
Claim 23
Independent Claim
98 words
A method for forming an isolation region for electrically isolating elements in a semiconductor substrate, comprising the steps of: (a) forming a metal silicide layer on the semiconductor substrate; (b) forming a resist layer on the metal silicide layer; (c) patterning the resist layer; (d) selectively etching the metal silicide layer and the semiconductor substrate by a reactive ion etching process using a mixture of chlorine-containing gas and oxygen gas to form a groove in the surface portion of the semiconductor substrate surrounding the periphery of the resist layer; and (e) forming an insulating layer in the groove.
Claim 24
Independent Claim
124 words
A method for forming an isolation region for electrically isolating elements in a semiconductor substrate, comprising the steps of: (a) forming a first insulating layer; (b) forming a metal silicide layer on the first insulating layer; (c) forming a resist layer on the metal silicide layer; (d) patterning the resist layer; (e) selectively etching the metal silicide layer by a reactive ion etching process using a mixture of chlorine-containing gas and oxygen gas; (f) etching the first insulating layer using the metal silicide layer as a masking film; (g) etching the semiconductor substrate using the etched insulating layer as a masking film to form a groove in the surface portion of the semiconductor substrate; and (h) forming a second insulating layer in the groove.
Claim 25
Independent Claim
124 words
A method for forming an isolation region for electrically isolating elements in a semiconductor substrate, comprising the steps of: (a) forming a first insulating layer; (b) forming a metal silicide layer on the first insulating layer; (c) forming a resist layer on the metal silicide layer; (d) patterning the resist layer; (e) selectively etching the metal silicide layer by a reactive ion etching process using a mixture of chlorine-containing gas and oxygen gas; (f) etching the first insulating layer using the metal silicide layer as a masking film; (g) etching the semiconductor substrate using the etched insulating layer as a masking film to form a groove in the surface portion of the semiconductor substrate; and (h) forming a second insulating layer in the groove.
Claim 26
Dependent Claim
31 words
A method according to claim 20, wherein said step (d) comprises selectively etching the metal silicide layer using a chlorine-containing gas selected from the group of carbon tetrachloride and boron trichloride.
References Cited (Backward Citations)
US4369565A
Cited
US4373990A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-08-14 | 1988-02-13 | 1988-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-08-14 | 1992-02-13 | 1992-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-08-14 | 1996-02-13 | 1996-08-14 | $7700.00 | Window Closed / Lapsed |