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US5355338A
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Redundancy circuit for semiconductor memory device
Assignee: SK Hynix Inc
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Filing: 1992-07-10
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Granted: 1994-10-11
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Expires: 2012-07-10
Abstract
Abstract A memory redundancy circuit using FLOTOX transistors instead of conventional link fuses and thus capable of redundancy programming even after the packaging of the chip. The redundancy circuit is capable of generating spare signals in order to use spare memory cells for particular addresses. The circuit includes: a reference line having a certain voltage level for generating spare signals; a reference voltage supplying circuit for supplying the required voltage to the reference line; two or more FLOTOX transistors connected to the reference line; and high voltage driving circuits provided for the FLOTOX transistors, and connected to address lines in such a manner as to supply the required voltage to the gates of the FLOTOX transistors for programming.
Inventors
- 👤 Seok W. Han
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:29
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C29/789
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
181 words
In a memory device having memory cells, some of which may be defective, two or more spare memory cells, address lines for receiving addresses of the memory cells and the two or more spare memory cells, and programmable and erasable transistors coupled to the address lines and the two or more spare memory cells, a method of selecting first and second spare memory cells, comprising the steps of: determining the address of a first defective memory cell; programming the programmable and erasable transistors with the address of the first defective memory cell, wherein the first spare memory cell is selected in response to the address of the first defective memory cell; determining the address of a second defective memory cell; erasing the programmable and erasable transistors; programming the programmable and erasable transistors with the addresses of the first and second defective memory cells, wherein the first spare memory cell is selected in response to the address of the first defective memory cell and the second spare memory cell is selected in response to the address of the second defective memory cell.
Claim 2
Dependent Claim
181 words
In a memory device having memory cells, some of which may be defective, two or more spare memory cells, address lines for receiving addresses of the memory cells and the two or more spare memory cells, and programmable and erasable transistors coupled to the address lines and the two or more spare memory cells, a method of selecting first and second spare memory cells, comprising the steps of: determining the address of a first defective memory cell; programming the programmable and erasable transistors with the address of the first defective memory cell, wherein the first spare memory cell is selected in response to the address of the first defective memory cell; determining the address of a second defective memory cell; erasing the programmable and erasable transistors; programming the programmable and erasable transistors with the addresses of the first and second defective memory cells, wherein the first spare memory cell is selected in response to the address of the first defective memory cell and the second spare memory cell is selected in response to the address of the second defective memory cell.
Claim 3
Dependent Claim
14 words
The method of claim 1, wherein the programmable and erasable transistors comprise EEPROM cells.
Claim 4
Dependent Claim
14 words
The method of claim 1, wherein the programmable and erasable transistors comprise FLOTOX transistors.
Claim 5
Dependent Claim
167 words
In a memory device having memory cells, some of which may be defective, two or more spare memory cells, address lines for receiving addresses of the memory cells and the two or more spare memory cells, and programmable and erasable transistors coupled to the address lines and the two or more spare memory cells, a method of selecting first and second spare memory cells, comprising the steps of: determining the address of a first defective memory cell; programming the programmable and erasable transistors with the address of the first defective memory cell; applying to the address lines the address of the first defective memory cell; selecting the first spare memory cell; determining the address of a second defective memory cell; erasing the programmable and erasable transistors; programming the programmable and erasable transistors with the addresses of the first and second defective memory cells; applying to the address lines the address of the first or second defective memory cell; and selecting the first or second spare memory cell.
Claim 6
Dependent Claim
167 words
In a memory device having memory cells, some of which may be defective, two or more spare memory cells, address lines for receiving addresses of the memory cells and the two or more spare memory cells, and programmable and erasable transistors coupled to the address lines and the two or more spare memory cells, a method of selecting first and second spare memory cells, comprising the steps of: determining the address of a first defective memory cell; programming the programmable and erasable transistors with the address of the first defective memory cell; applying to the address lines the address of the first defective memory cell; selecting the first spare memory cell; determining the address of a second defective memory cell; erasing the programmable and erasable transistors; programming the programmable and erasable transistors with the addresses of the first and second defective memory cells; applying to the address lines the address of the first or second defective memory cell; and selecting the first or second spare memory cell.
Claim 7
Dependent Claim
14 words
The method of claim 4, wherein the programmable and erasable transistors comprise EEPROM cells.
Claim 8
Dependent Claim
14 words
The method of claim 4, wherein the programmable and erasable transistors comprise FLOTOX transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-10 | 1998-04-11 | 1998-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-10 | 2002-04-11 | 2002-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-10 | 2006-04-11 | 2006-10-11 | $7700.00 | Window Closed / Lapsed |