US5344785A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming high speed, high voltage fully isolated bipolar transistors on a SOI substrate
Assignee: Frontgrade Colorado Springs LLC
•
Filing: 1993-06-03
•
Granted: 1994-09-06
•
Expires: 2013-06-03
Abstract
Abstract A method of manufacturing various types of silicon devices, such as complementary bipolar PNP and NPN transistors, in a Silicon On Insulator ("SOI") Integrated Circuit ("IC"), the SOI IC having a substrate, a buried insulating layer disposed above the substrate, and a silicon device layer disposed above the insulating layer. Vertical transistors may be formed in the device layer such that each transistor is fully dielectrically isolated from another and also from other similarly manufactured silicon devices in the silicon device layer.
Inventors
- 👤 Rick C. Jerome
- 👤 Diane R. Williams
- 👤 Kurt D. Humphrey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 10:09
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/041; H10D84/00; H10D84/60; H10D84/645; H10D84/67; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0145; H10W10/0147; H10W10/10; H10W10/17; Y; Y10; Y10S; Y10S148/00; Y10S148/085; Y10S148/15
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
301 words
A method of forming a complementary first and second transistor in a Silicon On Insulator ("SOI") Integrated Circuit ("IC"), the SOI IC having a substrate, a buried insulating layer superjacent the substrate, and a silicon device layer superjacent the buried insulating layer, the first and the second transistors formed in the silicon device layer such that the first transistor is dielectrically isolated from the second transistor, the method comprising the steps of: implanting an N doped buried conductor region in the device layer; implanting a P doped buried conductor region in the device layer; forming an epitaxial silicon layer superjacent the device layer, said epitaxial layer having a thickness of at least 2 microns, said epitaxial silicon layer having a dopant polarity; forming an N doped low resistance path between a surface of said epitaxial layer and said implanted N doped buried conductor region, and forming a P doped low resistance path between said surface of said epitaxial layer and said implanted P doped buried conductor region; forming a well in a portion of said epitaxial layer, said well superjacent at least one of said implanted N doped buried conductor region and said implanted P doped buried conductor region, said well having a doping polarity opposite that of said epitaxial silicon layer; forming a trench from said surface of said epitaxial layer down to the buried insulating layer, being disposed between said well and a remainder of said epitaxial layer so as to dielectrically isolate said well from said remainder of said epitaxial layer; and forming the first transistor in said well and the second transistor in said remainder of said epitaxial layer by implanting base regions in said well and in said remainder of said epitaxial layer of opposite polarities, and by forming emitter regions enclosed by said base regions.
Claim 2
Independent Claim
301 words
A method of forming a complementary first and second transistor in a Silicon On Insulator ("SOI") Integrated Circuit ("IC"), the SOI IC having a substrate, a buried insulating layer superjacent the substrate, and a silicon device layer superjacent the buried insulating layer, the first and the second transistors formed in the silicon device layer such that the first transistor is dielectrically isolated from the second transistor, the method comprising the steps of: implanting an N doped buried conductor region in the device layer; implanting a P doped buried conductor region in the device layer; forming an epitaxial silicon layer superjacent the device layer, said epitaxial layer having a thickness of at least 2 microns, said epitaxial silicon layer having a dopant polarity; forming an N doped low resistance path between a surface of said epitaxial layer and said implanted N doped buried conductor region, and forming a P doped low resistance path between said surface of said epitaxial layer and said implanted P doped buried conductor region; forming a well in a portion of said epitaxial layer, said well superjacent at least one of said implanted N doped buried conductor region and said implanted P doped buried conductor region, said well having a doping polarity opposite that of said epitaxial silicon layer; forming a trench from said surface of said epitaxial layer down to the buried insulating layer, being disposed between said well and a remainder of said epitaxial layer so as to dielectrically isolate said well from said remainder of said epitaxial layer; and forming the first transistor in said well and the second transistor in said remainder of said epitaxial layer by implanting base regions in said well and in said remainder of said epitaxial layer of opposite polarities, and by forming emitter regions enclosed by said base regions.
Claim 3
Dependent Claim
36 words
The method of claim 1, further comprising the step of: after said step of implanting an N doped buried conductor region in the device layer, forming a layer of implant screen oxide superjacent the device layer.
Claim 4
Dependent Claim
47 words
The method of claim 2, further comprising the step of: before said step of implanting a P doped buried conductor region in the device layer, performing a low temperature steam differential oxidation of said layer of implant screen oxide superjacent said implanted N doped buried conductor region.
Claim 5
Dependent Claim
39 words
The method of claim 3, further comprising the step of: before said step of forming, an epitaxial silicon layer superjacent the device layer, annealing said implanted N doped buried conductor region and said implanted P doped buried conductor region.
Claim 6
Dependent Claim
39 words
The method of claim 1, further comprising the step of: before said step of forming an epitaxial silicon layer superjacent the device layer, annealing said implanted N doped buried conductor region and said implanted P doped buried conductor region.
Claim 7
Dependent Claim
37 words
The method of claim 1, further comprising the step of: after said step of forming a well in said epitaxial layer, annealing said well, said N doped low resistance path, and said P doped low resistance path.
Claim 8
Dependent Claim
15 words
The method of claim 1, further comprising the step of: filling with a first oxide.
Claim 9
Dependent Claim
50 words
The method of claim 7, wherein said step of filling said trench with a first oxide comprises the steps of: filling a portion of the space in said trench along sidewalls of said trench with a second oxide; and filling the remaining space in said trench with a third oxide.
Claim 10
Dependent Claim
21 words
The method of claim 8, wherein at least one of said second and third oxides comprises tetra ethyl ortho silicate ("TEOS").
Claim 11
Dependent Claim
61 words
The method of claim 7, wherein said step of filling said trench with an oxide comprises the steps of: filling a portion of the space in said trench along sidewalls of said trench with a second oxide; filling a portion of the remaining space in said trench with third oxide; and filling the remaining space in said trench with a polysilicon.
Claim 12
Dependent Claim
21 words
The method of claim 10, wherein at least one of said second and third oxides comprises tetra ethyl ortho silicate ("TEOS").
Claim 13
Dependent Claim
15 words
The method of claim 7, wherein said first oxide comprises tetra ethyl ortho silicate ("TEOS").
Claim 14
Dependent Claim
32 words
The method of claim 7, further comprising the step of: after said step of filling said trench with an oxide, forming a cap on said trench by local oxidation of silicon ("LOCOS").
Claim 15
Dependent Claim
113 words
The method of claim 1, wherein said step of forming emitter regions comprises the steps of: depositing a layer of oxide on the surface of the IC abutting said base regions; etching said oxide layer; depositing a layer of polycrystalline silicon superjacent said oxide layer, said layer of polycrystalline silicon having regions of dopants; annealing the IC to diffuse said dopants in said polycrystalline silicon layer into said base regions to form emitters; and forming titanium silicide on the surface of said polycrystalline silicon layer such that a precision capacitor is formed between one of said regions of polycrystalline silicon, said deposited and etched oxide layer, and said N doped low resistance path.
Claim 16
Dependent Claim
196 words
The method of claim 1, further comprising the step of: after said step of forming a transistor in said well and in said epitaxial layer, forming electrical contacts to each of said base, said collector and said emitter of each of said transistors; depositing a layer of oxide superjacent said electrical contacts; forming a thin film resistor superjacent said layer of oxide deposited superjacent said electrical contacts; depositing a first layer of LTO oxide; etching said oxide layer superjacent said electrical contacts and said first LTO oxide layer at locations superjacent at least one of said electrical contacts; depositing a first level metal layer superjacent said first LTO oxide layer; etching said first level metal layer at locations to provide for electrical contact to said thin film resistor and at least one of said electrical contacts; depositing a second LTO oxide layer superjacent said first level metal layer; etching vias into said second LTO layer at locations; depositing a second level metal layer superjacent said second LTO oxide layer; depositing a layer of oxide and nitride superjacent said second level metal layer; and performing an alloy step of the IC at a temperature for a time.
Claim 17
Dependent Claim
18 words
The method of claim 15, wherein said thin film resistor comprises at least one of silicon and chromium.
Claim 18
Independent Claim
244 words
A method of forming complementary first and second transistors in a Silicon On Insulator ("SOI") for high voltage operation and having high speed and high breakdown voltage characteristics, said SOI comprising a substrate, a buried insulating layer superjacent said substrate, and a silicon device layer superjacent said buried insulating layer, said method comprising the steps of: implanting a P doped buried conductor regions in said silicon device layer; implanting an N doped buried conductor region in said silicon device layer; forming an epitaxial layer superjacent said silicon device layer, said epitaxial layer having a dopant polarity; forming an N doped low resistance path between a surface of said epitaxial layer and said implanted N doped buried conductor region; forming a P doped low resistance path between said surface of said epitaxial layer and said implanted P doped buried conductor region; forming a well in a portion of said epitaxial layer, said well superjacent at least one of said implanted N doped buried conductor region and said implanted P doped buried conductor region, said well having a doping polarity opposite that of said epitaxial layer; forming a trench from said surface of said epitaxial layer down to the buried insulating layer, said trench, being disposed between said well and a remainder of said epitaxial layer, dielectrically isolating said well from said remainder of said epitaxial layer; and forming the first transistor in said well and the second transistor in said remainder of said epitaxial layer.
Claim 19
Independent Claim
244 words
A method of forming complementary first and second transistors in a Silicon On Insulator ("SOI") for high voltage operation and having high speed and high breakdown voltage characteristics, said SOI comprising a substrate, a buried insulating layer superjacent said substrate, and a silicon device layer superjacent said buried insulating layer, said method comprising the steps of: implanting a P doped buried conductor regions in said silicon device layer; implanting an N doped buried conductor region in said silicon device layer; forming an epitaxial layer superjacent said silicon device layer, said epitaxial layer having a dopant polarity; forming an N doped low resistance path between a surface of said epitaxial layer and said implanted N doped buried conductor region; forming a P doped low resistance path between said surface of said epitaxial layer and said implanted P doped buried conductor region; forming a well in a portion of said epitaxial layer, said well superjacent at least one of said implanted N doped buried conductor region and said implanted P doped buried conductor region, said well having a doping polarity opposite that of said epitaxial layer; forming a trench from said surface of said epitaxial layer down to the buried insulating layer, said trench, being disposed between said well and a remainder of said epitaxial layer, dielectrically isolating said well from said remainder of said epitaxial layer; and forming the first transistor in said well and the second transistor in said remainder of said epitaxial layer.
Claim 20
Dependent Claim
55 words
The method of claim 17, wherein said forming the first transistor in said well and the second transistor in said remainder of said epitaxial layer comprises the steps of: implanting base regions in said well and in said remainder of said epitaxial layer of opposite polarities; and forming emitter regions enclosed by said base regions.
Claim 21
Dependent Claim
113 words
The method of claim 18, wherein said step of forming emitter regions comprises the steps of: depositing a layer of oxide on the surface of the IC abutting said base regions; etching said oxide layer; depositing a layer of polycrystalline silicon superjacent said oxide layer, said layer of polycrystalline silicon having regions of dopants; annealing the IC to diffuse said dopants in said polycrystalline silicon layer into said base regions to form emitters; and forming titanium silicide on the surface of said polycrystalline silicon layer such that a precision capacitor is formed between one of said regions of polycrystalline silicon, said deposited and etched oxide layer, and said N doped low resistance path.
Claim 22
Dependent Claim
63 words
The method of claim 17, further comprising the step of filling said trench with a first oxide, said filling said trench further comprising the steps of: filling a portion of the space in said trench along sidewalls of said trench with a second oxide; and filling the remaining space in said trench with at least one of a third oxide and a polysilicon.
References Cited (Backward Citations)
US4631803A
Cited
US4690729A
Cited
US5010378A
Cited
US4984039A
Cited
US4916511A
Cited
US4685199A
Cited
US4751561A
Cited
US4990991A
Cited
US5086011A
Cited
US4810667A
Cited
US4851078A
Cited
US5036021A
Cited
US4963505A
Cited
US4851366A
Cited
US4835115A
Cited
US4897703A
Cited
US4985744A
Cited
US4965213A
Cited
US4939099A
Cited
US5032529A
Cited
US4951102A
Cited
JPH0281438A
Cited
US4900689A
Cited
US5070388A
Cited
US5110749A
Cited
US5057895A
Cited
US5028557A
Cited
US5049513A
Cited
US5087580A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-05 | 1998-03-07 | 1998-09-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-05 | 2002-03-07 | 2002-09-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-05 | 2006-03-07 | 2006-09-06 | $7700.00 | Window Closed / Lapsed |