Trench gate VCMOS method of manufacture

Claim 1

A process for fabricating an integrated circuit comprising: selectively forming a plurality of laterally spaced first and second conductivity type buried regions in a first layer of semiconductor material, which is separated from a substrate by a base dielectric layer; forming a second layer of semiconductor material of said first conductivity type on said first layer; selectively introducing impurities of said second conductivity type into regions of said second layer juxtaposed said second conductivity type buried regions to form a plurality of first regions of said first conductivity type and second regions of said second conductivity type in said second layer; selectively introducing first and second conductivity type impurities into said second and first regions respectively to form third and fourth regions respectively; selectively introducing first and second conductivity type impurities into said fourth and third regions respectively to form fifth and sixth regions respectively; forming a plurality of vertical trenches in said first and second layers down to said base dielectric layer to form a plurality of islands having formed or to be formed said first and second conductivity buried regions, said first and second regions, said third and fourth regions, and said fifth and sixth regions laterally separated by said trenches; and forming a plurality of isolated gate segments in said trenches laterally isolated from said first and second layers and each other by dielectric isolation.