US4835115A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for forming oxide-capped trench isolation
Assignee: Texas Instruments Inc
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Filing: 1987-12-07
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Granted: 1989-05-30
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Expires: 2007-12-07
Abstract
Abstract A method of forming trench isolation is disclosed. A trench is etched, either through field oxide or not, into the substrate, using an oxide hard mask. Implant of a channel-stop is then performed through a dummy sidewall oxide, followed by stripping of the dummy oxide and regrowth of the sidewall oxide. A polysilicon layer is deposited into the trench and over the wafer, and is etched to clear from the surface, and overetched so that a recess is formed within the trench. The recess is then filled with a TEOS oxide layer deposited over the wafer surface, and the deposited oxide at the top of the trench is planarized with the surrounding surface.
Inventors
- 👤 Robert H. Eklund
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:06
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
132 words
A method for forming an isolation region for an integrated circuit at a surface of a semiconductor body, comprising: etching a trench into said semiconductor body at a selected location of said surface; forming a dummy dielectric layer over the sides of said trench; implanting the bottom of said trench with an impurity to form a channel stop; removing the dummy dielectric layer from the sides of said trench after said implanting step; forming a first dielectric layer over the sides of said trench, after said step of removing said dummy dielectric layer; forming a plug in said trench over said first dielectric layer, the top of said plug being below the top of said trench; forming a second dielectric layer over the top of said plug to substantially fill said trench.
Claim 2
Independent Claim
132 words
A method for forming an isolation region for an integrated circuit at a surface of a semiconductor body, comprising: etching a trench into said semiconductor body at a selected location of said surface; forming a dummy dielectric layer over the sides of said trench; implanting the bottom of said trench with an impurity to form a channel stop; removing the dummy dielectric layer from the sides of said trench after said implanting step; forming a first dielectric layer over the sides of said trench, after said step of removing said dummy dielectric layer; forming a plug in said trench over said first dielectric layer, the top of said plug being below the top of said trench; forming a second dielectric layer over the top of said plug to substantially fill said trench.
Claim 3
Dependent Claim
49 words
The method of claim 1, wherein said step of forming said plug comprises: depositing a layer of semiconductor material over said surface of said semiconductor body, said semiconductor layer filling said trench; etching said semiconductor layer in such a manner that the semiconductor layer is recessed into said trench.
Claim 4
Dependent Claim
20 words
The method of claim 2, wherein said etching step clears the semiconductor layer from said surface of said semiconductor body.
Claim 5
Dependent Claim
12 words
The method of claim 3, wherein said semiconductor layer comprises polycrystalline silicon.
Claim 6
Dependent Claim
67 words
The method of claim 2, wherein said step of forming said second dielectric layer comprises: depositing an oxide layer over said surface of said semiconductor body, said oxide layer filling the portion of said trench from which the semiconductor layer is recessed; and etching said oxide layer so that the top of said trench is substantially coplanar with the surface of said semiconductor body surrounding said trench.
Claim 7
Dependent Claim
50 words
The method of claim 1, further comprising: forming a buffer layer of polycrystalline silicon over said substrate; forming a hard mask layer over said layer of polycrystalline silicon; forming a photoresist pattern over said hard mask layer to define the location at which said isolation structure is to be formed.
Claim 8
Dependent Claim
77 words
The method of claim 6, further comprising: prior to said step of etching said trench, forming a field oxide layer over selected portions of said surface; and wherein said step of etching a trench comprises: etching said hard mask layer, said buffer layer and said field oxide structure to expose a location of said surface lying thereunder; and etching the portions of said surface which are not covered by said hard mask layer or said field oxide.
Claim 9
Dependent Claim
13 words
The method of claim 7, wherein said hard mask layer comprises silicon dioxide.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-29 | 1992-11-28 | 1993-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-29 | 1996-11-28 | 1997-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-29 | 2000-11-28 | 2001-05-30 | $7700.00 | Window Closed / Lapsed |