Semiconductor memory device having equalization terminated in direct response to a change in word line signal

Claim 2

A semiconductor memory device comprising: an array of memory cells arranged in rows and columns, a plurality of word lines connected to the rows of said memory cells, a plurality of bit lines connected to the columns of said memory cells, word line selections means operatively connected to said plurality of word lines and responsive to an externally applied address signal for selecting one of said word lines, bit line selection means operatively connected to said plurality of bit lines and responsive to said externally applied address signal for selecting at least one of said bit lines, and equalizing means operatively connected to said plurality of bit lines for equalizing said plurality of bit lines to a desired voltage level in direct response to a change of said externally applied address signal, and for terminating said equalizing in direct response to a change of a signal on said word line in accordance with the change of said address signal.

Claim 3

The semiconductor memory device according to claim 1, wherein said word line selection means comprises address buffer means for receiving said address signal, and word line selection decoder means connected to said address buffer means and for decoding said address signal.

Claim 4

The semiconductor memory device according to claim 1, wherein said bit line selection means comprises address buffer means for receiving said address signal, bit line selection decoder means connected to said address buffer means for decoding said address signal, and a bit line selection circuit connected to said bit line selection means.

Claim 5

The semiconductor memory device according to claim 3, further comprising a sense amplifier operatively connected to said bit line selection circuit and said equalizing means, wherein said equalizing means equalizes said sense amplifier to a desired voltage level.

Claim 6

The semiconductor memory device according to claim 4, further comprising output buffer means connected to said sense amplifier, wherein said equalizing means is operatively connected to a signal line between said sense amplifier and said output buffer means for equalizing said signal line to a desired voltage level.

Claim 7

The semiconductor memory device according to claim 4, wherein said equalizing means is operatively connected to a signal line between said bit line selection circuit and said sense amplifier for equalizing said signal line to a desired voltage level.

Claim 8

The semiconductor memory device according to claim 1, wherein said equalizing means comprises an address buffer receiving said address signals, first means operatively connected to said address buffer for sensing change in said address signal and generating an equalizing pulse in response thereto, and second means operatively connected to said word line selection means and said first means for sensing change in a signal of said word line and terminating said equalizing pulse generated by said first means.

Claim 9

A semiconductor memory device comprising: an array of memory cells arranged in rows and columns; a plurality of word lines connected to the rows of said memory cells; a plurality of bit lines connected to the columns of said memory cells; word line selection means operatively connected to said plurality of word lines and responsive to an externally applied address signal for selecting one of said word lines; bit line selection means operatively connected to said plurality of bit lines and response to said externally applied address signal for selecting at least one of said bit lines; address transition detection means for providing a predetermined signal in synchronization with a change of said externally applied address signal; word line selection detection means operatively connected to said word line selection means and responsive to the selected word line for providing a signal indicating selection of one of said word line; gate means receiving said predetermined signal and said signal indicating selection of a word line and providing an output pulse signal; and equalizing means operatively connected to said plurality of bit lines for equalizing said plurality of bit lines to a desired voltage level in response to said output pulse signal, wherein an equalizing period begins in response to a first change of said output pulse signal and ends in response to a second change of said output pulse signal.

Claim 10

A semiconductor memory device comprising: an array of memory cells arranged in rows and columns; a plurality of word lines connected to the rows of said memory cells; a plurality of bit lines connected to the columns of said memory cells; word line selection means operatively connected to said plurality of word lines and responsive to an externally applied address signal for selecting one of said word lines; bit line selection means operatively connected to said plurality of bit lines and response to said externally applied address signal for selecting at least one of said bit lines; address transition detection means for providing a predetermined signal in synchronization with a change of said externally applied address signal; word line selection detection means operatively connected to said word line selection means and responsive to the selected word line for providing a signal indicating selection of one of said word line; gate means receiving said predetermined signal and said signal indicating selection of a word line and providing an output pulse signal; and equalizing means operatively connected to said plurality of bit lines for equalizing said plurality of bit lines to a desired voltage level in response to said output pulse signal, wherein an equalizing period begins in response to a first change of said output pulse signal and ends in response to a second change of said output pulse signal.

Claim 11

A semiconductor memory device comprising: an array of memory cells arranged in rows and columns, a plurality of word lines connected to the rows of said memory cells, a plurality of bit lines connected to the columns of said memory cells, word line selection means operatively connected to said plurality of word lines and responsive to an externally applied address signal for selecting one of said word lines, bit line selection means operatively connected to said plurality bit lines and responsive to said externally applied address signal for selecting at least one of said bit lines, and equalizing means operatively connected to said plurality of bit lines for equalizing said plurality of bit lines to a desired voltage level in direct response to a change of said externally applied address signal, and for terminating said equalizing in direct response to a change of a signal on said word line in accordance with the change of said address signal, wherein said word line selection means includes a word line selection decoder and a word line address transition detector connected between said word line selection means and said array of memory cells, and said equalizing means comprises means to sense change in said address signal for generating an equalizing pulse, and means to sense change in a signal of said word line for terminating said equalizing means.

Claim 12

A semiconductor memory device comprising: an array of memory cells arranged in rows and columns, a plurality of word lines connected to the rows of said memory cells, a plurality of bit lines connected to the columns of said memory cells, word line selection means operatively connected to said plurality of word lines and responsive to an externally applied address signal for selecting one of said word lines, bit line selection means operatively connected to said plurality bit lines and responsive to said externally applied address signal for selecting at least one of said bit lines, and equalizing means operatively connected to said plurality of bit lines for equalizing said plurality of bit lines to a desired voltage level in direct response to a change of said externally applied address signal, and for terminating said equalizing in direct response to a change of a signal on said word line in accordance with the change of said address signal, wherein said word line selection means includes a word line selection decoder and a word line address transition detector connected between said word line selection means and said array of memory cells, and said equalizing means comprises means to sense change in said address signal for generating an equalizing pulse, and means to sense change in a signal of said word line for terminating said equalizing means.