US4564925A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory
Assignee: Hitachi Ltd
•
Filing: 1983-09-23
•
Granted: 1986-01-14
•
Expires: 2003-09-23
Abstract
Abstract A semiconductor memory has dynamic memory cells, such as one-MOS transistor cells, a detector circuit which detects changes in applied address signals, and a timing generator circuit which receives detection outputs of the detector circuit. When the address signals are changed, various timing signals are responsively produced from the timing generator circuit. In response to the timing signals generated in succession, data lines to which the memory cells are coupled are first precharged, and one of the memory cells is selected after the precharge of the data lines. Data delivered from the selected memory cell to the data line is amplified when the operation of a sense amplifier is started. The amplified data is supplied to an external terminal through a column switch, a main amplifier, an output amplifier, etc., which are similarly operated in succession. Since the semiconductor memory of this arrangement forms a pseudo-static memory, it requires only a small number of external timing signals. In order to obtain a desirable pseudo-static memory, a data line precharge level is equalized to half of the supply voltage level, and the sense amplifier is constructed of a CMOS-FET latch circuit. As a result, the period of time from the change of the address signals until the delivery of the output data can be sufficiently shortened. It is therefore possible to form a pseudo-static memory which is, in effect, regarded as a static memory.
Inventors
- 👤 Yoshiaki Onishi, deceased
- 👤 administratrix by Junko Onishi
- 👤 Hiroshi Kawamoto
- 👤 Tokumasa Yasui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:58
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
254 words
A semiconductor memory comprising: a plurality of dynamic memory cells; a first selector circuit which receives first address signals and which selects ones of said plurality of dynamic memory cells specified by the first address signals, and the time of which is controlled by a first timing signal; a plurality of pairs of data lines connected to said dynamic memory cells so that each pair of data lines is respectively provided with a potential difference in accordance with the data read out from a selected dynamic memory cell; a plurality of sense amplifiers each of which has a pair of input and output terminals that are coupled to a corresponding pair of data lines, the respective sense amplifiers having their operations controlled by second timing signals; a first precharge circuit which is coupled to said plurality of pairs of data lines and operates so as to precharge said data lines at a potential intermediate between binary signals to be stored in the dynamic memory cells in accordance with a third timing signal; a first detector circuit including means connected to receive said first address signals for detecting level changes in the first address signals; and a timing generator circuit connected to receive the detection outputs of said first detector circuit, and including means for generating said third timing signal for operating said first precharge circuit, said first timing signal for operating said first selector circuit after stopping the operation of said first precharge circuit, and said second timing signals for operating said sense amplifiers.
Claim 2
Dependent Claim
254 words
A semiconductor memory comprising: a plurality of dynamic memory cells; a first selector circuit which receives first address signals and which selects ones of said plurality of dynamic memory cells specified by the first address signals, and the time of which is controlled by a first timing signal; a plurality of pairs of data lines connected to said dynamic memory cells so that each pair of data lines is respectively provided with a potential difference in accordance with the data read out from a selected dynamic memory cell; a plurality of sense amplifiers each of which has a pair of input and output terminals that are coupled to a corresponding pair of data lines, the respective sense amplifiers having their operations controlled by second timing signals; a first precharge circuit which is coupled to said plurality of pairs of data lines and operates so as to precharge said data lines at a potential intermediate between binary signals to be stored in the dynamic memory cells in accordance with a third timing signal; a first detector circuit including means connected to receive said first address signals for detecting level changes in the first address signals; and a timing generator circuit connected to receive the detection outputs of said first detector circuit, and including means for generating said third timing signal for operating said first precharge circuit, said first timing signal for operating said first selector circuit after stopping the operation of said first precharge circuit, and said second timing signals for operating said sense amplifiers.
Claim 3
Dependent Claim
37 words
A semiconductor memory according to claim 1, wherein said each dynamic memory cell is constructed of a MOSFET whose gate is used as a selecting terminal, and a charge holding capacitor which is coupled to said MOSFET.
Claim 4
Dependent Claim
38 words
A semiconductor memory according to claim 2, wherein said precharge circuit is constructed of MOSFETs each of which short-circuits a corresponding pair of data lines in response to said third timing signal supplied from said timing generator circuit.
Claim 5
Dependent Claim
19 words
A semiconductor memory according to claim 3, wherein said each sense amplifier is constructed of a complementary MOSFET circuit.
Claim 6
Dependent Claim
186 words
A semiconductor memory according to claim 4, further comprising: a pair of common data lines; a second selector circuit including means connected to receive applied second address signals for coupling said common data lines to the pair of data lines specified by the second address signals among said plurality of pairs of data lines with an operation timing which is controlled by a fourth timing signal; a second precharge circuit which is coupled to said common data lines and operates to precharge said common data lines in accordance with a fifth timing signal; a main amplifier which is coupled to said common data lines; means for controlling the operation timing of said main amplifier in response to a sixth timing signal; a second detector circuit including means connected to receive said second address signals for detecting changes in the second address signals; and said timing generator circuit including means responsive to outputs of said first and second detector circuits for generating said fourth, fifth and sixth timing signals for controlling operation timings of said second selector circuit, said second precharge circuit and said main amplifier, respectively.
Claim 7
Dependent Claim
18 words
A semiconductor memory according to claim 5, wherein said main amplifier is constructed of a complementary MOSFET circuit.
Claim 8
Dependent Claim
36 words
A semiconductor memory according to claim 5, wherein said second precharge circuit functions to charge said pair of common data lines at a potential intermediate between binary signals to be stored in the dynamic memory cells.
Claim 9
Dependent Claim
25 words
A semiconductor memory according to claim 3, wherein said first detector circuit and said timing generator circuit are constructed of static type complementary MOSFET circuits.
Claim 10
Dependent Claim
68 words
A semiconductor memory according to claim 3, wherein said each of said sense amplifiers is constructed of a static type complementary MOSFET latch circuit, a first switching MOSFET which is interposed between one power feed terminal of said latch circuit and a power source terminal, and a second switching MOSFET which is interposed between a remaining power feed terminal of said latch circuit and another power source terminal.
References Cited (Backward Citations)
DE2430690A1
Cited
DE2658655A1
Cited
DE2734361A1
Cited
US4339809A
Cited
US4338679A
Cited
DE3101520A1
Cited
DE3217493A1
Cited
US4472792A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-01-13 | 1989-07-15 | 1990-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-01-13 | 1993-07-15 | 1994-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-01-13 | 1997-07-15 | 1998-01-14 | $7700.00 | Window Closed / Lapsed |