Row driver circuit for semiconductor memory

Claim 2

A row driver circuit for driving row lines in a semiconductor memory, comprising: a row driver transistor for each of the row lines of the semiconductor memory, each of the row driver transistors having a drain terminal, a source terminal and a gate terminal, the source terminal of each row driver transistor connected to the corresponding row line; a row decoder circuit connected to receive a plurality of first address bits for generating a drive signal when said row decoder is selected by said first address bits; a transition detector circuit connected to receive address bits provided to said semiconductor memory for generating a transition signal upon a change of state for any one of said address bits; means responsive to said drive signal and said transition signal for precharging the gate terminals of a group of said row driver transistors corresponding to said row decoder circuit; and means for decoding a plurality of second address bits to generate a clock signal for transfer to the drain terminal of a selected one of the row driver transistors within said group such that the clock signal is capacitively coupled to increase the voltage on the precharged gate terminal to thereby charge the row line connected to the selected row driver transistor.

Claim 3

The row driver circuit recited in claim 1 wherein said means for decoding a plurality of second address bits comprises a clock decoder circuit connected to receive said second address bits and said transition signal for generating one of a plurality of clock signals, said clock signals connected for transmission respectively to the drain terminals of the row driver transistors within said group.

Claim 4

A row driver circuit for driving row lines in a semiconductor memory, comprising: a row driver transistor for each of the row lines of the semiconductor memory, each of the row driver transistors having a drain terminal, a source terminal and a gate terminal, the source terminal of each row driver transistor connected to the corresponding row line; a row decoder circuit for receiving a plurality of first address bits and generating a drive signal at the output terminal thereof when said row decoder circuit is selected by said first address bits; a transition detector circuit connected to receive said first address bits for generating a transition signal having a preset duration active state upon detection of a change of state for any one of said first address bits; means responsive to said drive signal for holding at a fixed potential a group of row lines corresponding to said row line decoder; means responsive to said transition signal for selectively connecting the output terminal of said row decoder to the gate terminals of a corresponding group of said row driver transistors wherein the gate terminals of said row driver transistors are charged when said first address bits select said row decoder circuit and the active state of said transition signal is generated; and a clock generator circuit connected to receive a plurality of second address bits for generating any one of a plurality of clock signals at respective output terminals of said clock generator circuit, said output terminals connected respectively to the drain terminals of said row driver transistors within said group for capacitively coupling the voltage on the precharged gate terminals of the corresponding row driver transistor to charge the corresponding row line to at least the voltage of the clock signal.

Claim 5

A row driver circuit for driving row lines in a semiconductor memory, comprising: a row driver transistor for each of the row lines of the semiconductor memory, each of the row driver transistors having a drain terminal, a source terminal and a gate terminal, the source terminal of each row driver transistor connected to the corresponding row line; a row decoder circuit for receiving a plurality of first address bits and generating a drive signal at the output terminal thereof when said row decoder circuit is selected by said first address bits; a transition detector circuit connected to receive said first address bits for generating a transition signal having a preset duration active state upon detection of a change of state for any one of said first address bits; means responsive to said drive signal for holding at a fixed potential a group of row lines corresponding to said row line decoder; means responsive to said transition signal for selectively connecting the output terminal of said row decoder to the gate terminals of a corresponding group of said row driver transistors wherein the gate terminals of said row driver transistors are charged when said first address bits select said row decoder circuit and the active state of said transition signal is generated; and a clock generator circuit connected to receive a plurality of second address bits for generating any one of a plurality of clock signals at respective output terminals of said clock generator circuit, said output terminals connected respectively to the drain terminals of said row driver transistors within said group for capacitively coupling the voltage on the precharged gate terminals of the corresponding row driver transistor to charge the corresponding row line to at least the voltage of the clock signal.

Claim 6

The row driver circuit recited in claim 3 wherein said means responsive to said drive signal for holding at a fixed potential comprises: an inverter circuit having an input and an output terminal, the input terminal thereof connected to the output terminal of said row decoder circuit; and a pull down transistor for each of said row lines, each of said pull down transistors having the drain terminal thereof connected to the corresponding row line, the source terminals thereof connected to a common node and the gate terminals thereof connected to the output terminal of said inverter.

Claim 7

The row driver circuit recited in claim 3 wherein said means responsive to said transition signal for selectively connecting comprises: a first transistor having the gate terminal thereof connected to the output terminal of said row decoder; the drain terminal thereof coupled through an impedance element to a fixed voltage node, and the source terminals thereof connected to receive said transition signal; and an isolation transistor for each of said row lines, each of said isolation transistors having the drain terminal thereof connected to the output terminal of said row decoder circuit, the source terminal thereof connected to the gate terminal of the corresponding row driver transistor and the gate terminal thereof connected to the drain terminal of said first transistor.

Claim 8

A row driver circuit for driving row lines in a semiconductor memory, comprising: a row driver transistor for each of the row lines of the semiconductor memory, each of the row driver transistors having a drain terminal, a source terminal and a gate terminal, the source terminal of each row driver transistor connected to the corresponding row line; a row decoder circuit for receiving a plurality of first address bits and generating a drive signal at the output terminal thereof when said row decoder circuit is selected by said first address bits; a transition detector circuit for each of said first address bits, said transition detector circuits connected to receive said first address bits and generate a transition signal having a preset duration active state upon detection of a change of state for any one of said first address bits; an inverter circuit having an input and an output terminal, the input terminal thereof connected to the output terminal of said row decoder circuit; a pull down transistor for each of said row lines, each of said pull down transistors having the drain terminal thereof connected to the corresponding row line, the source terminals thereof connected to a common node and the gate terminals thereof connected to the output terminal of said inverter; a first transistor having the gate terminal thereof connected to the output terminal of said row decoder, the drain terminal thereof coupled through an impedance element to a fixed voltage node, and the source terminals thereof connected to receive said transition signal; an isolation transistor for each of said row lines, each of said isolation transistors having the drain terminal thereof connected to the output terminal of said row decoder circuit, the source terminal thereof connected to the gate terminal of the corresponding row driver transistor and the gate terminal thereof connected to the drain terminal of said first transistor; and a clock decoder circuit connected to receive a plurality of second address bits for generating any one of a plurality of clock signals at the respective output terminals thereof, said output terminals connected respectively to the drain terminals of said row driver transistors for capacitively coupling the voltage on the precharged gate terminals of the corresponding row driver transistor to activate the corresponding row driver transistor to charge the corresponding row line to the voltage of the clock signal.

Claim 9

A row driver circuit for driving row lines in a semiconductor memory, comprising: a row driver transistor for each of the row lines of the semiconductor memory, each of the row driver transistors having a drain terminal, a source terminal and a gate terminal, the source terminal of each row driver transistor connected to the corresponding row line; a row decoder circuit for receiving a plurality of first address bits and generating a drive signal at the output terminal thereof when said row decoder circuit is selected by said first address bits; a transition detector circuit for each of said first address bits, said transition detector circuits connected to receive said first address bits and generate a transition signal having a preset duration active state upon detection of a change of state for any one of said first address bits; an inverter circuit having an input and an output terminal, the input terminal thereof connected to the output terminal of said row decoder circuit; a pull down transistor for each of said row lines, each of said pull down transistors having the drain terminal thereof connected to the corresponding row line, the source terminals thereof connected to a common node and the gate terminals thereof connected to the output terminal of said inverter; a first transistor having the gate terminal thereof connected to the output terminal of said row decoder, the drain terminal thereof coupled through an impedance element to a fixed voltage node, and the source terminals thereof connected to receive said transition signal; an isolation transistor for each of said row lines, each of said isolation transistors having the drain terminal thereof connected to the output terminal of said row decoder circuit, the source terminal thereof connected to the gate terminal of the corresponding row driver transistor and the gate terminal thereof connected to the drain terminal of said first transistor; and a clock decoder circuit connected to receive a plurality of second address bits for generating any one of a plurality of clock signals at the respective output terminals thereof, said output terminals connected respectively to the drain terminals of said row driver transistors for capacitively coupling the voltage on the precharged gate terminals of the corresponding row driver transistor to activate the corresponding row driver transistor to charge the corresponding row line to the voltage of the clock signal.