Dynamic random access memory with fet equalization of bit lines

Claim 2

A dynamic random access memory comprising: memory cells arranged in a matrix of rows and columns, a plurality of word lines each associated with a respective row and a plurality of bit line pairs each associated with a respective column, each bit line pair comprising a plurality of divided bit line pair sections, sense amplifying means for amplifying a potential difference of each said divided bit line pair section so that one divided bit line of a respective section is at a first potential and the other divided bit line of said respective section is at a second potential, and an equalizing means in each divided bit line pair section for coupling together bit lines of each divided bit line pair section in response to an equalizing signal, said equalizing means comprising first switching means for receiving said equalizing signal; second switching means for coupling said divided bit line pair sections of each bit line pair, and timing controller means for applying activation signals to the equalizing means of each divided bit line pair section prior to a sensing operation, said timing controller means comprising means for continuing equalization of a first divided bit line pair section of a given bit line pair when a sensing operation begins in a second bit line pair section of said given bit line pair.

Claim 3

A dynamic random access memory in accordance with claim 1, wherein said first and second sense amplifying means are sense amplifiers formed by N-channel FETs and sense amplifiers formed by P-channel FETs.

Claim 4

A dynamic random access memory in accordance with claim 1, wherein said equalizing means are N-channel FETs.

Claim 5

A dynamic random access memory in accordance with claim 1, wherein said switching means are N-channel FETs.

Claim 6

A dynamic random access memory as recited in claim 1, wherein said timing controller means further comprises first means for terminating an activation signal applied to said equalization means and second means for delaying termination of an activation signal applied to the equalization means of said first divided bit line pair section of said given bit line pair unitl after the sensing operation in said second bit line pair section of said given bit line pair has begun.

Claim 7

A dynamic random access memory as recited in claim 1, wherein only one of said divided bit line pairs included in one of said memory array blocks is connected to bus lines within said divided bit line pairs included in said plurality of memory cell array blocks.

Claim 8

A dynamic random access memory as recited in claim 1, wherein said equalizing means stop equalization immediately before starting of sensing operation in said memory cell array blocks including said equalizing means.

Claim 9

A dynamic random access memory as recited in claim 1, wherein said timing controller means includes means for controlling said switching means to stop connection of adjacent ones of said memory cell blocks in an interval between a predetermined time subsequent to the start of a row address select signal and a predetermined time during the period of activation of the first and second sense amplifying means subsequent to the start thereof.

Claim 10

A dynamic random access memory as recited in claim 1, wherein said memory cell block different from said memory cell array block including said equalizing means adjacent to said memory cell array block including said equalizing means.

Claim 11

A dynamic random access memory comprising: a plurality of memory cell array blocks each including a plurality of word lines a plurality of divided bit line pairs, and memory cells each connected to one of said divided bit line pairs and to one of said word lines, first sense amplifying means for amplifying a potential difference of each said divided bit line pair so that one divided bit line is at a first potential, and second sense amplifying means for amplifying a potential difference of each said divided bit line pair so that the other divided bit line is at a second potential, and equalizing means for equalizing respective ones of said divided bit line pairs, said equalizing means comprising FET means for coupling bit lines of respective divided bit line pairs, each said FET means having gate electrode means for receiving equalizing signal; switching means for coupling said divided bit line pairs of adjacent ones of said memory cell array blocks; timing controller means coupled to said equalizing means for controlling respective timings of said equalizing signal applied to each said FET means of said equalizing means to stop said equalizing means selectively and at different times among said memory cell blocks such that each said equalizing means is stopped after sensing operation is started in a memory cell array block different from the memory cell array block including said equalizing means; wherein only one of said divided bit line pairs included in one of said memory array blocks is connected to bus lines within said divided bit line pairs included in said plurality of memory cell array blocks.

Claim 12

A dynamic random access memory comprising: a plurality of memory cell array blocks each including a plurality of word lines a plurality of divided bit line pairs, and memory cells each connected to one of said divided bit line pairs and to one of said word lines, first sense amplifying means for amplifying a potential difference of each said divided bit line pair so that one divided bit line is at a first potential, and second sense amplifying means for amplifying a potential difference of each said divided bit line pair so that the other divided bit line is at a second potential, and equalizing means for equalizing respective ones of said divided bit line pairs, said equalizing means comprising FET means for coupling bit lines of respective divided bit line pairs, each said FET means having gate electrode means for receiving equalizing signal; switching means for coupling said divided bit line pairs of adjacent ones of said memory cell array blocks; timing controller means coupled to said equalizing means for controlling respective timings of said equalizing signal applied to each said FET means of said equalizing means to stop said equalizing means selectively and at different times among said memory cell blocks such that each said equalizing means is stopped after sensing operation is started in a memory cell array block different from the memory cell array block including said equalizing means; wherein only one of said divided bit line pairs included in one of said memory array blocks is connected to bus lines within said divided bit line pairs included in said plurality of memory cell array blocks.

Claim 13

A dynamic random access memory comprising: a plurality of memory cell array blocks each including a plurality of word lines a plurality of divided bit line pairs, and memory cells each connected to one of said divided bit line pairs and to one of said word lines, first sense amplifying means for amplifying a potential difference of each said divided bit line pair so that one divided bit line is at a first potential, and second sense amplifying means for amplifying a potential difference of each said divided bit line pair so that the other divided bit line is at a second potential, and equalizing means for equalizing respective ones of said divided bit lines pairs, said equalizing means comprising FET means for coupling bit lines of respective divided bit line pairs, each said FET means having gate eletrode means for receiving an equalizing signal; switching means for coupling said divided bit line pairs of adjacent ones of said memory cell array blocks; timing controller means coupled to said equalizing means for controlling respective timings of said equalizing signal applied to each said FET means of said equalizing means to stop said equalinzing means selectively and at different times among said memory cell blocks such that each equalizing means is stopped after sensing operation is started in a memory cell array block different from the memory cell array block including said equalizing means; wherein, said equalizing means stop equalization immediately before starting of sensing operation in said memory cell array blocks including said equalizing means.

Claim 14

A dynamic random access memory comprising: a plurality of memory cell array blocks each including a plurality of word lines a plurality of divided bit line pairs, and memory cells each connected to one of said divided bit line pairs and to one of said word lines, first sense amplifying means for amplifying a potential difference of each said divided bit line pair so that one divided bit line is at a first potential, and second sense amplifying means for amplifying a potential difference of each said divided bit line pair so that the other divided bit line is at a second potential, and equalizing means for equalizing respective ones of said divided bit lines pairs, said equalizing means comprising FET means for coupling bit lines of respective divided bit line pairs, each said FET means having gate eletrode means for receiving an equalizing signal; switching means for coupling said divided bit line pairs of adjacent ones of said memory cell array blocks; timing controller means coupled to said equalizing means for controlling respective timings of said equalizing signal applied to each said FET means of said equalizing means to stop said equalinzing means selectively and at different times among said memory cell blocks such that each equalizing means is stopped after sensing operation is started in a memory cell array block different from the memory cell array block including said equalizing means; wherein, said equalizing means stop equalization immediately before starting of sensing operation in said memory cell array blocks including said equalizing means.

Claim 15

A dynamic random access memory comprising: a plurality of memory cell array blocks each including a plurality of word lines a plurality of divided bit line pairs, and memory cells each connected to one of said divided bit line pairs and to one of said word lines, first sense amplifying means for amplifying a potential difference of each said divided bit line pair so that one divided bit line is at a first potential, and second sense amplifying means for amplifying a potential difference of each said divided bit line pair so that the other divided bit line is at a second potential, and equalizing means for equalizing respective ones of said divided bit line pairs, said equalizing means comprising FET means for coupling bit lines of respective divided bit line pairs, each said FET means having gate electrode means for receiving an equalizing signal; switching means for coupling said divided bit line pairs of adjacent ones of said memory cell array blocks; timing controller means coupled to said equalizing means for controlling respective timings of said equalizing signal applied to each said FET means of said equalizing means to stop said equalizing means selectively and at different times among said memory cell blocks such that each said equalizing means is stopped after sensing operation is started in a memory cell array block different from the memory cell array block including said equalizing means; said timing controller means includes means for controlling said switching means to stop connection of adjacent ones of said memory cell array blocks in an interval between a predetermined time subsequent to the start of a row address select signal and a predetermined time during the period of activation of the first and second sense amplifying means subsequent to the start thereof.

Claim 16

A dynamic random access memory comprising: a plurality of memory cell array blocks each including a plurality of word lines a plurality of divided bit line pairs, and memory cells each connected to one of said divided bit line pairs and to one of said word lines, first sense amplifying means for amplifying a potential difference of each said divided bit line pair so that one divided bit line is at a first potential, and second sense amplifying means for amplifying a potential difference of each said divided bit line pair so that the other divided bit line is at a second potential, and equalizing means for equalizing respective ones of said divided bit line pairs, said equalizing means comprising FET means for coupling bit lines of respective divided bit line pairs, each said FET means having gate electrode means for receiving an equalizing signal; switching means for coupling said divided bit line pairs of adjacent ones of said memory cell array blocks; timing controller means coupled to said equalizing means for controlling respective timings of said equalizing signal applied to each said FET means of said equalizing means to stop said equalizing means selectively and at different times among said memory cell blocks such that each said equalizing means is stopped after sensing operation is started in a memory cell array block different from the memory cell array block including said equalizing means; said timing controller means includes means for controlling said switching means to stop connection of adjacent ones of said memory cell array blocks in an interval between a predetermined time subsequent to the start of a row address select signal and a predetermined time during the period of activation of the first and second sense amplifying means subsequent to the start thereof.

Claim 17

A dynamic random access memory comprising: a plurality of memory cell array blocks each including a plurality of word lines a plurality of divided bit line pairs, and memory cells each connected to one of said divided bit line pairs and to one of said word lines, first sense amplifying means for amplifying a potential difference of each said divided bit line pair so that one divided bit line is at a first potential, and second sense amplifying means for amplifying a potential difference of each said divided bit line pair so that the other divided bit line is at a second potential, and equalizing means for equalizing respective ones of said divided bit line pairs, said equalizing means comprising FET means for coupling bit lines of respective divided bit line pairs, each said FET means having gate electrode means for receiving an equalizing signal; switching means for coupling said divided bit line pairs of adjacent ones of said memory cell array blocks; timing controller means coupled to said equalizing means for controlling respective timings of said equalizing signal applied to each said FET means of said equalizing means to stop said equalizing means selectively and at different times among said memory cell blocks such that each said equalizing means is stopped after sensing operation is started in a memory cell array block different from the memory cell array block including said equalizing means; wherein, said memory cell block different from said memory cell array block including said equalizing means is adjacent to said memory cell array block including said equalizing means.

Claim 18

A dynamic random access memory comprising: a plurality of memory cell array blocks each including a plurality of word lines a plurality of divided bit line pairs, and memory cells each connected to one of said divided bit line pairs and to one of said word lines, first sense amplifying means for amplifying a potential difference of each said divided bit line pair so that one divided bit line is at a first potential, and second sense amplifying means for amplifying a potential difference of each said divided bit line pair so that the other divided bit line is at a second potential, and equalizing means for equalizing respective ones of said divided bit line pairs, said equalizing means comprising FET means for coupling bit lines of respective divided bit line pairs, each said FET means having gate electrode means for receiving an equalizing signal; switching means for coupling said divided bit line pairs of adjacent ones of said memory cell array blocks; timing controller means coupled to said equalizing means for controlling respective timings of said equalizing signal applied to each said FET means of said equalizing means to stop said equalizing means selectively and at different times among said memory cell blocks such that each said equalizing means is stopped after sensing operation is started in a memory cell array block different from the memory cell array block including said equalizing means; wherein, said memory cell block different from said memory cell array block including said equalizing means is adjacent to said memory cell array block including said equalizing means.

Claim 23

A method of reducing noise generation in a dynamic random access memory as recited in claim 15, wherein said equalizing means stop equalization immediately before starting of sensing operation in said memory cell array block including said equalizing means.