EP0071245A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1982-07-27
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Granted: —
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Expires: 2002-07-27
Abstract
Abstract A semiconductor memory device includes memory cells (MC-11 to MC-MN) arranged in a matrix array, a plurality of pairs of bit lines (BO-1 to BO-M, B1-1 to B1-M), each pair of bit lines being connected to the memory cells on the same column, a plurality of pairs of switching MOS transistors (TR01 to TROM, TR11 to TR1 M), each pair of MOS transistors being connected between a power source terminal (VD) and each pair of bit lines, and a precharge control circuit for supplying a control signal to the gates of the switching MOS transistors. This memory device further includes delay circuits (DL1 to DLM) connected in series with each other, and the delay circuits delay the control signal from the precharge control circuit (2) and supply the control signal to the gates of the switching MOS transistors (TR01 to TROM, TR11 to TRIM) at different timings.
Inventors
- 👤 Hajime Kai
- 👤 Kiyofumi Ochii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 23:59
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/12; G11C5/00; G11C5/06; G11C5/063
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
75 words
A semiconductor memory device comprising a plurality of semiconductor memory cells (MC-11 to MC- M N) arranged in a plurality of columns, and a plurality of bit lines (BO-1 to BO-M, Bl-1 to Bl-M) respectively connected to the memory cells on the same column, characterized by further comprising means connected to said plurality of bit lines (BO-1 to BO-M, Bl-1 to Bl-M) for causing operating currents to flow through the bit lines in different phases.
Claim 2
Dependent Claim
75 words
A semiconductor memory device comprising a plurality of semiconductor memory cells (MC-11 to MC- M N) arranged in a plurality of columns, and a plurality of bit lines (BO-1 to BO-M, Bl-1 to Bl-M) respectively connected to the memory cells on the same column, characterized by further comprising means connected to said plurality of bit lines (BO-1 to BO-M, Bl-1 to Bl-M) for causing operating currents to flow through the bit lines in different phases.
Claim 3
Dependent Claim
88 words
A semiconductor memory device according to claim 1, characterized in that said means includes a power source terminal (VD), a control signal generating circuit (2), a plurality of switching circuits (PC-1 to PC -M) each connected between a corresponding one of said plurality of bit lines (BO-1 to BO-M, Bl-1 to Bl-M) and said power source terminal, and delay means (DL1 to DL ( M -1)) for setting said switching circuits conductive at different timings in response to the control signal from said control signal generating circuit (2).
Claim 4
Dependent Claim
28 words
A semiconductor memory device according to claim 2, characterized in that said delay means is composed of delay circuits (DLl to DL(M-1)) connected in series with each other.
Claim 5
Dependent Claim
78 words
A semiconductor memory device according to claim 1, 2 or 3, characterized by further comprising a plurality of sense amplifier circuits (SA-1 to SA-M) respectively connected to said plurality of bit lines (BO-1 to BO-M, Bl-1 to Bl-M), an activation signal generating circuit (6), and another delay means (D(M+1) to D(2M-1)) for energizing said plurality of sense amplifier circuits (SA-1 to SA-M) at different timings in response to an activation signal from said activation signal generating circuit (6).
Claim 6
Dependent Claim
29 words
A semiconductor memory device according to claim 4, characterized in that said another delay means is composed of delay circuits (D(M+1) to D(2M-1)) connected in series with each other.
Claim 7
Dependent Claim
60 words
A semiconductor memory device according to claim 5, characterized in that said plurality of bit lines are arranged in the form of plural pairs and the bit lines of each pair are commonly connected to the memory cells (MC-11 to MC-MN) on the same column and to a corresponding one of said plurality of sense amplifier circuits (SA-1 to SA-M).
Claim 8
Dependent Claim
64 words
A semiconductor memory device according to claim 1, 2 or 3, characterized in that said plurality of bit lines are arranged in the form of a plural pairs and the bit lines of each pair are commonly connected to the memory cells (MC-11 to MC-MN) on the same column and to a corresponding one of said plurality of sense amplifier circuits (SA-1 to SA-M).
Claim 9
Dependent Claim
90 words
A semiconductor memory device according to claim 1, characterized by further comprising a plurality of sense amplifier circuits (SA-1 to SA-M) respectively connected to said plurality of bit lines (BO-1 to BO-M, B l-1 to Bl-M), and an activation signal generating circuit (6) for generating an activation signal for energizing the sense amplifier circuits (SA-1 to SA-M), and in that said means is delay means (DL(M-1) to DL(2M-1)) for delaying the activation signal from said activation signal generating circuit and energizing said plurality of sense amplifier circuits at different timings.
Claim 10
Dependent Claim
28 words
A semiconductor memory device according to claim 8, characterized in that said delay means is composed of delay circuits (DL(M+l) to DL(2M-1)) connected in series with each other.
References Cited (Backward Citations)
No citation records indexed.
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