Method and apparatus for selectively precharging column lines of a memory

Claim 2

A memory array having a plurality of intersecting row lines and column lines in which data bits are output on selected column lines and in which a column line is precharged before an output is read on that column line, wherein the memory array is divided into at least four adjacent side-by-side portions, wherein a first portion is adjacent to a second portion, the second portion is between the first portion and a third portion, and the third portion is between the second portion and a fourth portion; and wherein the column lines of the first and third portions are precharged when a predetermined address signal is in a first logic state and column lines of the second and fourth portions are precharged when the predetermined address signal is in a second logic state.

Claim 3

The memory array of claim 1 further comprising a first set of amplifiers for receiving data bits from the first portion when the predetermined address signal is in the first logic state and from the second portion when the predetermined address signal is in the second logic state.

Claim 4

The memory array of claim 2 further comprising a second set of amplifiers for receiving data bits from the third portion when the predetermined address signal is in the first logic state and from the fourth portion when the predetermined address is in the second logic state.

Claim 5

The memory array of claim 3 wherein each portion of the memory array provides four data bits of a byte and wherein each of the first and second sets of amplifiers comprises four sense amplifiers.

Claim 6

The memory array of claim 4 wherein the four sense amplifiers of the first set of amplifiers sense the logic states of the four data bits provided by the first portion when the predetermined address signal is in the first logic state and the logic states of the four data bits provided by the second portion when the predetermined address signal is in the second logic state.

Claim 7

The memory array of claim 5 wherein the four sense amplifiers of the second set of amplifiers sense the logic states of the four data bits provided by the third portion when the predetermined address signal is in the first logic state and the logic states of the four data bits provided by the fourth portion when the predetermined address signal is in the second logic state.

Claim 8

The memory array of claim 6 wherein precharging occurs in response to an equalization pulse.

Claim 9

In a memory array having a plurality of intersecting row lines and column lines in which data bits are output on selected column lines and in which a column line is precharged before an output is read on that column line, a method for precharging the column lines comprising the steps of: dividing the memory into at least four consecutively numbered, adjacent side-by-side portions; and precharging the column lines of odd-numbered portions when a control signal is in a first logic state and precharging the column lines of even-numbered portions when the control signal is in a second logic state.

Claim 10

In a memory array having a plurality of intersecting row lines and column lines in which data bits are output on selected column lines and in which a column line is precharged before an output is read on that column line, a method for precharging the column lines comprising the steps of: dividing the memory into at least four consecutively numbered, adjacent side-by-side portions; and precharging the column lines of odd-numbered portions when a control signal is in a first logic state and precharging the column lines of even-numbered portions when the control signal is in a second logic state.

Claim 11

The method of claim 8, wherein the precharging is further characterized as occuring for a duration of an equalization pulse.

Claim 12

A memory circuit, comprising: a memory array having a plurality of intersecting row lines and column lines in which data bits are output on selected column lines and in which a column line is precharged before an output is read on that column line, wherein the memory array is divided into at least four adjacent side-by-side portions, wherein a first portion is adjacent to a second portion, a fourth portion is adjacent to a third portion, the second portion is between the first and third portions, and the third portion is between the second and fourth portions; and precharging means for precharging the column lines of the first and third portions when a predetermined address signal is in a first logic state and precharging the column lines of the second and fourth portions when the predetermined address signal is in a second logic state.

Claim 13

A memory circuit, comprising: a memory array having a plurality of intersecting row lines and column lines in which data bits are output on selected column lines and in which a column line is precharged before an output is read on that column line, wherein the memory array is divided into at least four adjacent side-by-side portions, wherein a first portion is adjacent to a second portion, a fourth portion is adjacent to a third portion, the second portion is between the first and third portions, and the third portion is between the second and fourth portions; and precharging means for precharging the column lines of the first and third portions when a predetermined address signal is in a first logic state and precharging the column lines of the second and fourth portions when the predetermined address signal is in a second logic state.

Claim 14

The memory circuit of claim 10 wherein the precharging by the precharging means occurs in response to an equalization pulse.

Claim 15

The memory circuit of claim 11 further comprising: first reading means for reading data from the first portion when the predetermined address signal is in a first logic state and reading data from the second portion when the predetermined address signal is in a second logic state; and second reading means for reading data from the third portion when the predetermined address signal is in a first logic state and reading data from the fourth portion when the predetermined address signal is in a second logic state.

Claim 16

The memory circuit of claim 12 wherein the first and second reading means are further characterized as providing outputs which correspond to the data which is read.

Claim 17

The memory circuit of claim 13 further comprising output pads which receive the outputs of the first and second reading means on uninterrupted conductor lines.

Claim 18

The memory circuit of claim 14 wherein the conductor lines are metal.