Asynchronous row and column control

Claim 2

A memory circuit which has a plurality of bit line pairs which are selected by a column address and a plurality of word line lines which are selected by a row address, the bit line pairs being selectively coupled to a common data line by column decoders as determined by the column address and the word lines being selectively enabled by a row decoder as determined by the row address, a memory cell being located at each intersection of the bit line pairs and word lines, comprising: column detection means means providing a column transition signal for at least a predetermined time duration following a column address transition; and decoupling means for decoupling at least one selected bit line pair from the common data line in response to the column transition signal.

Claim 3

The memory circuit of claim 1 further comprising: precharging means for precharging the bit lines while the column transition signal is provided.

Claim 4

In a memory circuit which has a plurality of bit line pairs which are selected by a column address and a plurality of word line lines which are selected by a row address, the bit lines pairs being selectively coupled to a common data line by column decoders as determined by the column address and the word lines being selectively enabled by a row decoder as determined by the row address, a memory cell being located at each intersection of the bit line pairs and word lines, a method comprising the steps of: detecting a row address transition; and disabling the row decoder for at least a predetermined time duration following the detection of the row address transition.

Claim 5

In a memory circuit which has a plurality of bit line pairs which are selected by a column address and a plurality of word line lines which are selected by a row address, the bit lines pairs being selectively coupled to a common data line by column decoders as determined by the column address and the word lines being selectively enabled by a row decoder as determined by the row address, a memory cell being located at each intersection of the bit line pairs and word lines, a method comprising the steps of: detecting a row address transition; and disabling the row decoder for at least a predetermined time duration following the detection of the row address transition.

Claim 6

The method of claim 3 further comprising the steps of: detecting a column address transition; and decoupling at least one selected bit line pair from the common data line for at least a second predetermined time duration following the detection of the column address transition.

Claim 7

In a memory circuit which has a plurality of bit line pairs which are selected by a column address and a plurality of word line lines which are selected by a row address, the bit line pairs being selectively coupled to a common data line by column decoders as determined by the column address and the word lines being selectively enabled by a row decoder as determined by the row address, a memory cell being located at each intersection of the bit line pairs and word lines, a method comprising the steps of: detecting a column address transition; and decoupling at least one selected bit line pair from the common data line for at least a second predetermined time duration following the detection of the column address transition.

Claim 8

In a memory circuit which has a plurality of bit line pairs which are selected by a column address and a plurality of word line lines which are selected by a row address, the bit line pairs being selectively coupled to a common data line by column decoders as determined by the column address and the word lines being selectively enabled by a row decoder as determined by the row address, a memory cell being located at each intersection of the bit line pairs and word lines, a method comprising the steps of: detecting a column address transition; and decoupling at least one selected bit line pair from the common data line for at least a second predetermined time duration following the detection of the column address transition.

Claim 9

A memory circuit which has a plurality of bit line pairs which are selected by a column address and a plurality of word lines which are selected by a row address, the bit line pairs being selectively coupled to a common data line by column decoders as determined by the column address and the word lines being selectively enabled by a row decoder as determined by the row address, a memory cell being located at each intersection of the bit line pairs and word lines, comprising: row detection means for generating a row transition signal in response to detecting a row address transition; and disabling means for disabling the row decoder in response to the row transition signal.

Claim 10

A memory circuit which has a plurality of bit line pairs which are selected by a column address and a plurality of word lines which are selected by a row address, the bit line pairs being selectively coupled to a common data line by column decoders as determined by the column address and the word lines being selectively enabled by a row decoder as determined by the row address, a memory cell being located at each intersection of the bit line pairs and word lines, comprising: row detection means for generating a row transition signal in response to detecting a row address transition; and disabling means for disabling the row decoder in response to the row transition signal.

Claim 11

The memory circuit of claim 6 further comprising: column detection means for generating a column transition signal in response to detecting a column address transition; and decoupling means for decoupling the bit lines from the common data line in response to the column transition signal.

Claim 12

The memory circuit of claim 7 further comprising: precharging means for precharging the bit lines while the bit lines are decoupled from the common data line; and equalizing means for equalizing the bit lines while the word line drivers are disabled.

Claim 13

The memory circuit of claim 8 wherein the disabling means is further characterized as providing a row decoder disable signal to the row decoder in response to a row address transition to disable the row decoder.

Claim 14

The memory circuit of claim 9 further comprising a cycle end timer, coupled to the column and row detection means and to the disable means, for causing the disable means to provide the row disable signal a predetermined time period following a row or column address transition unless reset by another row or column address transition which occurs before expiration of the predetermined time period.

Claim 15

The memory circuit of claim 10 further comprising equilibration means for equilibrating the data lines in response to a column or row address transition.

Claim 16

A memory circuit which has a plurality of bit line pairs which are selected by a column address and a plurality of word line lines which are selected by a row address, the bit line pairs being selectively coupled to a common data line by column decoders as determined by the column address and the word lines being selectively enabled by a row decoder as determined by the row address, a memory cell being located at each intersection of the bit line pairs and word lines, comprising: row detection means for generating a row transition signal in response to detecting a row address transition; disabling means for disabling the row decoder in response to the row transition signal; a cycle end timer, coupled to the row detection means and to the disable means, for causing the disable means to disable the row decoder after a predetermined time period following a row address transition unless reset by another row address transition which occurs before expiration of the predetermined time period.

Claim 17

A memory circuit which has a plurality of bit line pairs which are selected by a column address and a plurality of word line lines which are selected by a row address, the bit line pairs being selectively coupled to a common data line by column decoders as determined by the column address and the word lines being selectively enabled by a row decoder as determined by the row address, a memory cell being located at each intersection of the bit line pairs and word lines, comprising: row detection means for generating a row transition signal in response to detecting a row address transition; disabling means for disabling the row decoder in response to the row transition signal; a cycle end timer, coupled to the row detection means and to the disable means, for causing the disable means to disable the row decoder after a predetermined time period following a row address transition unless reset by another row address transition which occurs before expiration of the predetermined time period.

Claim 18

The memory circuit of claim 12 further comprising column detection means for generating a column transition signal in response to detecting a column address transition; and decoupling means for decoupling the bit lines from the common data line in response to the column transition signal.

Claim 19

The memory circuit of claim 13 further comprising equilibration means for equilibrating the data lines in response to a column or row address transition.

Claim 20

A memory having a plurality of memory cells coupled to word lines and bit line pairs at intersections thereof, each memory cell providing data to the bit line pair to which it is coupled when the word line to which it is coupled is enabled, comprising: row decoder means, coupled to the word lines, for disabling a selected word line as determined by a row address; column decoder means, coupled to the bit line pairs, for coupling a data line pair to a selected bit line pair as determined by a column address and for preventing any bit line pair from being coupled to the data line pair in response to receiving a column disable signal; and column detection means, coupled to the column decoder means, for providing the column disable signal for at least a predetermined time duration following a transition of the column address.

Claim 21

A memory having a plurality of memory cells coupled to word lines and bit line pairs at intersections thereof, each memory cell providing data to the bit line pair to which it is coupled when the word line to which it is coupled is enabled, comprising: row decoder means, coupled to the word lines, for disabling a selected word line as determined by a row address; column decoder means, coupled to the bit line pairs, for coupling a data line pair to a selected bit line pair as determined by a column address and for preventing any bit line pair from being coupled to the data line pair in response to receiving a column disable signal; and column detection means, coupled to the column decoder means, for providing the column disable signal for at least a predetermined time duration following a transition of the column address.

Claim 22

The memory of claim 15, wherein the row decoder means is further characterized as being prevented from enabling any word lines in response to receiving a row disable signal, further comprising: row detection means, coupled to the row decoder means, for providing the row disable signal for at least a second predetermined time duration following the transition of the row address.

Claim 23

A memory having a plurality of memory cells coupled to word lines and bit line pairs at intersections thereof, each memory cell providing data to the bit line pair to which it is coupled when the word line to which it is coupled is enabled, comprising: row decoder means, coupled to the word lines, for enabling a selected word line as determined by a row address, said row decoder means characterized as being prevented from enabling any word lines in response to receiving a row disable signal; column decoder means, coupled to the bit line pairs, for coupling a data line pair to a selected bit line pair as determined by a column address; and row detection means, coupled to the row decoder means, for providing the row disable for at least a predetermined time duration following a transition of the row address.

Claim 24

A memory having a plurality of memory cells coupled to word lines and bit line pairs at intersections thereof, each memory cell providing data to the bit line pair to which it is coupled when the word line to which it is coupled is enabled, comprising: row decoder means, coupled to the word lines, for enabling a selected word line as determined by a row address, said row decoder means characterized as being prevented from enabling any word lines in response to receiving a row disable signal; column decoder means, coupled to the bit line pairs, for coupling a data line pair to a selected bit line pair as determined by a column address; and row detection means, coupled to the row decoder means, for providing the row disable for at least a predetermined time duration following a transition of the row address.