EP0121208A2
Expired / Lapsed
EP
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Static type semiconductor memory circuit
Assignee: Toshiba Corp
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Filing: 1984-03-26
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Granted: —
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Expires: 2004-03-26
Abstract
Abstract A static type memory circuit has a plurality of memory cells (MC-11 to MC-MN) arranged in a matrix form, a plurality of word lines (WL-1 to WL-N) and a plurality of pairs of bit lines (BL1-1 to BL1-M, BLO-1 to BLO-M), each oftheword lines (WL-1 to WL-N) being coupled to memory cells on a corresponding row, each pair of the bit lines (BL1-1 to BL1-M, BLO-1 to BLO-M) being commonly coupled to memory cells on a corresponding column, a sense amplifier circuit (SA-1 to SA-M) coupled to the bit lines, a row decoder (20) for energizing one of the word lines in response to row address data, a transition detecting circuit (14) for generating an output signal when the row address data is changed, a control signal generator (16) for causing the sense amplifier circuit (SA-1 to SA-M) to be active in response to the output signal from the transition detecting circuit (14), and a precharge control circuit (18) for controlling precharging of the bit lines in response to the output signal from the transition detecting circuit (14). The precharge control circuit (18) precharges the bit line to "1" level potential when the sense amplifier circuit (SA-1 to SA-M) is rendered nonoperative in response to the output signal from the control signal generator(16), and stops the precharging operation in response to an output signal from the transition detecting circuit (14).
Inventors
- 👤 Kiyofumi Ochii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 08:26
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
288 words
A static type semiconductor memory circuit having a plurality of memory cells (MC-11 to MC-MN), a plurality of word lines (WL-1 to WL-N) and bit lines (BLl-1 to BL1-M, BLO-1 to BLO-M), respectively, which are coupled to said plurality of memory cells (MC-11 to MC-MN), sense amplifier means (SA-1 to SA-M) coupled to said plurality of bit lines (BL1-1 to BL1-M, BLO-1 to BLO-M); transition detecting means (14) for generating an output signal when said transition detecting means (14) detects that address data has changed, word line selection means (20) for selecting at least one of said plurality of word lines (WL-1 to WL-M) in accordance with the address data, sense amplifier control means (16) for supplying a control signal to said sense amplifier means (SA-1 to SA-M) to set said sense amplifier means (SA-1 to SA-M) in an operative mode for a predetermined period of time in response to an output signal from said transition detecting means (14), and potential setting means (18, TR12-1 to TR12-M, TR13-1 to TR13-M) for controlling potentials at said plurality of bit lines (BL1-1 to BL1-M, BLO-1 to BLO-M) in response to the output signal from said transition detecting means(14), characterized by further comprising data holding means (12) for holding readout data from said memory cells (MC-11 to MC-MN) through said bit lines (BL1-1 to BL1-M, BLO-I to BLO-M), and characterized in that said potential setting means (18, TR12-1 to TR12-M, TR13-1 to TR13-M) sets the potentials at said bit lines (BLl-1 to BL1-M, BLO-1 to BLO-M) to an initial potential level within a given memory cycle after the data read out from said memory cells (MC-11 to MC-MN) in the given memory cycle are held in said data holding means (12).
Claim 2
Dependent Claim
288 words
A static type semiconductor memory circuit having a plurality of memory cells (MC-11 to MC-MN), a plurality of word lines (WL-1 to WL-N) and bit lines (BLl-1 to BL1-M, BLO-1 to BLO-M), respectively, which are coupled to said plurality of memory cells (MC-11 to MC-MN), sense amplifier means (SA-1 to SA-M) coupled to said plurality of bit lines (BL1-1 to BL1-M, BLO-1 to BLO-M); transition detecting means (14) for generating an output signal when said transition detecting means (14) detects that address data has changed, word line selection means (20) for selecting at least one of said plurality of word lines (WL-1 to WL-M) in accordance with the address data, sense amplifier control means (16) for supplying a control signal to said sense amplifier means (SA-1 to SA-M) to set said sense amplifier means (SA-1 to SA-M) in an operative mode for a predetermined period of time in response to an output signal from said transition detecting means (14), and potential setting means (18, TR12-1 to TR12-M, TR13-1 to TR13-M) for controlling potentials at said plurality of bit lines (BL1-1 to BL1-M, BLO-1 to BLO-M) in response to the output signal from said transition detecting means(14), characterized by further comprising data holding means (12) for holding readout data from said memory cells (MC-11 to MC-MN) through said bit lines (BL1-1 to BL1-M, BLO-I to BLO-M), and characterized in that said potential setting means (18, TR12-1 to TR12-M, TR13-1 to TR13-M) sets the potentials at said bit lines (BLl-1 to BL1-M, BLO-1 to BLO-M) to an initial potential level within a given memory cycle after the data read out from said memory cells (MC-11 to MC-MN) in the given memory cycle are held in said data holding means (12).
Claim 3
Dependent Claim
138 words
A circuit according to claim 1, characterized in that said potential setting means (18, TR12 - 1 to TR12-M, TR13-1 to TR13-M) comprises a plurality of switching means (TR12-1 to TR12-M, TR13-1 to TR13-M) each of which has one end coupled to a power supply terminal (VC) and the other end coupled to a corresponding one of said bit lines (BL1-1 to BL1-M, BLO-1 to BLO-M), and a precharge control circuit (18) for keeping said switching means (TR12-1 to TR12-M, TR13-1 to TR13-M) in a conductive state within a predetermined period of time in response to the output signals from said transition detecting means (14) and said sense amplifier control means (16) after said sense amplifier means (SA-1 to SA-M) is rendered nonoperative and before a next transition detection signal is generated from said transition detecting means (14).
Claim 4
Dependent Claim
130 words
A circuit according to claim 1, characterized in that a pair of bit lines (BL-1 to BL1-M, BLO-1 to BLO-M) are coupled to said memory cells (MC-11 to MC-MN) of each column; said potential setting means comprises load resistive means (TR12, TR13) coupled between said pair of bit lines (BL1-1 to BLI-M, BL0-1 to BLO-M) and said power supply terminal, switching means (TR16) coupled between said pair of bit lines (BL1-1 to BL1-M, BLO-1 to BLO-M), and a precharge control circuit (18) for keeping on said switching means (TR16) in a conductive state within.a predetermined period of time after said transition detecting means (14) and said sense amplifier means (SA-1 to SA-M) are rendered nonoperative and before a next transition detection signal is generated from said transition detecting means (14).
Claim 5
Dependent Claim
39 words
.A circuit according to claim 1, 2 or 3, characterized in that said word line selection means (20) selects one of said word lines (WL-1 to WL-N) in response to a transition detection signal from said transition detecting.means (14).
Claim 6
Dependent Claim
94 words
A circuit according to claim 1 or 2, characterized in that said data holding means comprises at least one data line (DL1, DLO) coupled to said bit lines (BL1-1 to BL1-M, BLO-1 to BLO-M) through a switching circuit (TR20-1 to TR20-M, TR21-1 to TR21-M), a potential setting circuit (TR22, TR23) for setting said at least one data line (DLO, DLO) at a predetermined potential in response to an output signal from said precharge control circuit (18), and a data holding circuit (12) for holding memory data sent through said at least one data line.
Claim 7
Dependent Claim
16 words
-.A circuit according to claim 5, characterized 'in that said data holding circuit comprises a flip-flop.
Claim 8
Dependent Claim
44 words
A circuit according to claim 5, characterized in that said data holding circuit comprises a latch (31, 32) for latching data appearing on said at least one data line (DL1, DLO) in response to the output signal from said sense amplifier control means (16).
Claim 9
Dependent Claim
58 words
A circuit according to any one of claims 2 to 7, characterized in that said precharge control circuit (18) comprises an RS flip-flop which is set in response to the transition detection signal supplied from said transition detecting means (14) and which is reset in response to the control signal supplied from said sense amplifier control means (16).
References Cited (Backward Citations)
No citation records indexed.
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