Synchronous dynamic random access memory

Claim 1

A synchronous dynamic random-access memory that provides data output in response to multiplexed address signals, a first control signal, a second control signal, and a clock signal, comprising: a memory cell array having a plurality of memory cells; an address input circuit for latching said address signals on a first transition of said clock signal selected by said first control signal to generate an X-address, and on a second transition of said clock signal selected by said second control signal to generate a Y-address; a decoding circuit coupled to said memory cell array and said address input circuit, for selecting at least one memory cell in said memory cell array according to said X-address and said Y-address; and an output circuit coupled to said memory cell array, for outputting data from said memory cells in synchronization with said clock, wherein said output circuit comprises: a multiple data latch circuit for simultaneously latching data read from a plurality of said memory cells; a consecutive output control circuit for selecting data latched in said multiple data latch circuit, different data being selected in different clock cycles; and a tri-state output circuit for externally outputting data selected by said consecutive output control circuit.