Block oriented random access memory able to perform a data read, a data write and a data refresh operation in one block-access time

Claim 2

A digital data memory system realized as a single integrated circuit comprising: block oriented digital data storage means (50) wherein each block includes D dynamic data storage elements and has a unique address, where D is a positive integer; an input port (DI 0 →DI 3 ) for applying D data values to the memory system; control means (22,30,31,34,36), coupled to said input port and to said block oriented digital data storage means, for storing D data values applied via said input port into one of said blocks during a time interval T WR , retrieving D data values from one of said blocks during a time interval T RD , and refreshing at least D data values held in one of said blocks during a time interval T RF where the time intervals T wR , T RD and T RF are mutually exclusive; a source (22) of data output clock signal having a maximum frequency of f e ; and data output means (54A-54D), coupled to said block oriented digital data storage means, having a parallel input port for receiving the D data values provided by said block oriented digital data storage means during said time interval T RD , and a serial output port for providing the received D data values sequentially in synchronism with D successive pulses of said data output clock signal; wherein the amount of time represented by the sum of the lengths of the time intervals T WR , T RD and T RF is not greater than an amount of time represented by a mathematical expression, D/f c .

Claim 3

The digital data memory system set forth in claim 1 wherein the time intervals T wR , T RD and T RF each represent an amount of time substantially equal to one-fourth of the amount of time represented by the expression D/f e .

Claim 4

The digital data memory system set forth in claim 2 wherein said control means refreshes data values held in said digital data storage mean not more than once in any time interval having a length represented by a mathematical expression 2 * D/f c .

Claim 5

A digital data memory system comprising: block oriented digital data storage means wherein each block has a unique address and includes D dynamic data storage elements for holding D data values, where D is a positive integer; a serial input port for applying data values sequentially to the memory system; a source of data input clock signal having a maximum frequency of f c ; input buffer means, coupled to said input port, including first shift register means having a serial input port and a parallel output port, for storing D data values applied to said memory system input port synchronous with D successive pulses of said input clock signal, and for providing said D stored data values via said parallel output port; control means, coupled to said input buffer means and to said block oriented digital data storage means, for conditioning said data storage means, during a time interval T WR , to store the D data values provided by said input buffer means into one of said blocks, for conditioning said data storage means, during a time interval TR O , to provide D data values from one of said blocks, and for conditioning said data storage means, during a time interval T RF , to refresh at least D data values held in one of said blocks, where the time intervals T WR , T RD and T RF are mutually exclusive and where the sum of the lengths of the time intervals T WR , T RD and T RF is not greater than an amount of time represented by a mathematical expression D/f c ; a source of data output clock signal; and output buffer means, coupled to said digital data storage means, including second shift register means having a parallel input port and a serial output port, for storing, in parallel, the D data values provided by said digital data storage means during the time interval T RD , and for providing said D data values stored in said second shift register means, in sequence via said serial output port, synchronous with D successive pulses of said data output clock signal.

Claim 6

A digital data memory system comprising: block oriented digital data storage means wherein each block has a unique address and includes D dynamic data storage elements for holding D data values, where D is a positive integer; a serial input port for applying data values sequentially to the memory system; a source of data input clock signal having a maximum frequency of f c ; input buffer means, coupled to said input port, including first shift register means having a serial input port and a parallel output port, for storing D data values applied to said memory system input port synchronous with D successive pulses of said input clock signal, and for providing said D stored data values via said parallel output port; control means, coupled to said input buffer means and to said block oriented digital data storage means, for conditioning said data storage means, during a time interval T WR , to store the D data values provided by said input buffer means into one of said blocks, for conditioning said data storage means, during a time interval TR O , to provide D data values from one of said blocks, and for conditioning said data storage means, during a time interval T RF , to refresh at least D data values held in one of said blocks, where the time intervals T WR , T RD and T RF are mutually exclusive and where the sum of the lengths of the time intervals T WR , T RD and T RF is not greater than an amount of time represented by a mathematical expression D/f c ; a source of data output clock signal; and output buffer means, coupled to said digital data storage means, including second shift register means having a parallel input port and a serial output port, for storing, in parallel, the D data values provided by said digital data storage means during the time interval T RD , and for providing said D data values stored in said second shift register means, in sequence via said serial output port, synchronous with D successive pulses of said data output clock signal.

Claim 7

The digital data memory system set forth in claim 4 wherein the time intervals T WR , T RD and T RF each represent an amount of time substantially equal to one-fourth of the amount of time represented by the expression D/f c .

Claim 8

The digital data memory system set forth in claim 5 wherein said control means conditions said data storage means to refresh data values held in said digital data storage means not more than once in any time interval having a length represented by a mathematical expression 2*D/f c .

Claim 9

A digital video memory system comprising: a source of system clock signal having a frequency of f e ;

Claim 10

A digital video memory system comprising: a source of system clock signal having a frequency of f e ;

Claim 11

block oriented pixel storage means wherein each block has a unique address and includes D dynamic data storage elements for holding D pixel values, where D is a positive integer. a serial input port for applying pixel values sequentially to the memory system; a serial output port for providing sequential pixel values from the memory system; means, coupled to said source of system clock signal for generating a pixel input clock signal having a maximum frequency of f e ; input buffer means, coupled to said input port, including first shift register means having a serial input port and a parallel output port, for storing D pixel values applied to said memory system input port synchronous with D successive pulses of said pixel input clock signal, and for providing said D stored pixel values via said parallel output port; control means, coupled to said input buffer means and to said pixel storage means, for conditioning said pixel storage means, during a time interval, T WR , to store the D pixel values provided by said input buffer means into one of said blocks, for conditioning said pixel storage means, during a time interval, T RD , to provide D pixel values from one of said blocks, and for conditioning said pixel storage means during a time interval, T RF , to refresh at least D pixel values held in one of said blocks, where the time intervals T WR , T RD and T RF are mutually exclusive and where the sum of the lengths of the time intervals T WR , T RD and T RF is not greater than an amount of time represented by a mathematical expression, D/f e ; means, coupled to said source of system clock signal for generating a pixel output clock signal having a maximum frequency of f c ; and output buffer means, coupled to said pixel storage means, including second shift register means having a parallel input port and a serial output port, for storing, in parallel, the D pixel values provided by said pixel storage means during the time interval T RD , and for providing the D pixel values stored in said second shift register means, in sequence, via said memory system output port, synchronous with D successive pulses of said output clock signal.

Claim 12

block oriented pixel storage means wherein each block has a unique address and includes D dynamic data storage elements for holding D pixel values, where D is a positive integer. a serial input port for applying pixel values sequentially to the memory system; a serial output port for providing sequential pixel values from the memory system; means, coupled to said source of system clock signal for generating a pixel input clock signal having a maximum frequency of f e ; input buffer means, coupled to said input port, including first shift register means having a serial input port and a parallel output port, for storing D pixel values applied to said memory system input port synchronous with D successive pulses of said pixel input clock signal, and for providing said D stored pixel values via said parallel output port; control means, coupled to said input buffer means and to said pixel storage means, for conditioning said pixel storage means, during a time interval, T WR , to store the D pixel values provided by said input buffer means into one of said blocks, for conditioning said pixel storage means, during a time interval, T RD , to provide D pixel values from one of said blocks, and for conditioning said pixel storage means during a time interval, T RF , to refresh at least D pixel values held in one of said blocks, where the time intervals T WR , T RD and T RF are mutually exclusive and where the sum of the lengths of the time intervals T WR , T RD and T RF is not greater than an amount of time represented by a mathematical expression, D/f e ; means, coupled to said source of system clock signal for generating a pixel output clock signal having a maximum frequency of f c ; and output buffer means, coupled to said pixel storage means, including second shift register means having a parallel input port and a serial output port, for storing, in parallel, the D pixel values provided by said pixel storage means during the time interval T RD , and for providing the D pixel values stored in said second shift register means, in sequence, via said memory system output port, synchronous with D successive pulses of said output clock signal.

Claim 13

The digital video memory system set forth in claim 7 wherein the time intervals T WR , T RD and T RF each represent an amount of time substantially equal to one-fourth of the amount of time represented by the expression D/f c .

Claim 14

The digital video memory system set forth in claim 8 wherein: f c is substantially equal to 14.32 MHz; D is substantially equal to 32; and each of the time intervals T WR , T RD and T RFS pans eight periods of said system clock signal.

Claim 15

The digital video memory system set forth in claim 9 wherein said control means conditions said pixel storage means to refresh data values held in said pixel storage means, not more than once in any 64 successive periods of said system clock signal.