Patent US5323060A successfully refreshed from Google Patents.
US5323060A
Expired / Lapsed
US
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Multichip module having a stacked chip arrangement
Assignee: Round Rock Research LLC
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Filing: 1993-06-02
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Granted: 1994-06-21
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Expires: 2013-06-02
Abstract
Abstract A multichip module includes: a) a multichip module substrate; b) a first chip, the first chip having opposed base and bonding faces, the base face being adhered to the multichip module substrate, the first chip bonding face including a central area and a plurality of bonding pads peripheral to the central area; c) a second chip, the second chip having opposed base and bonding faces, the second chip bonding face including a central area and a plurality of peripheral bonding pads; d) a first/second adhesive layer interposed between and connecting the first chip bonding face and the second chip base face, the first/second adhesive layer having a thickness and a perimeter, the perimeter being positioned within the central area inside of the peripheral bonding pads; e) a plurality of first loop bonding wires bonded to and between the respective first chip bonding pads and the multichip module substrate, the respective first bonding wires having outwardly projecting loops of a defined loop height, the thickness of the adhesive layer being greater than the loop height to displace the second chip base face in a non-contacting relationship above and with respect to the first wires; and f) a plurality of second loop bonding wires bonded to and between the respective second chip bonding pads and the multichip module substrate.
Inventors
- 👤 Rich Fogal
- 👤 Michael B. Ball
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:35
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/071; H10W72/075; H10W90/00; H10W72/073; H10W72/07331; H10W72/07337; H10W72/07351; H10W72/07352; H10W72/07551; H10W72/07554; H10W72/30; H10W72/321; H10W72/351; H10W72/353; H10W72/354; H10W72/50; H10W72/531; H10W72/536; H10W72/5363; H10W72/5366; H10W72/541; H10W72/5445; H10W72/5453; H10W72/547; H10W72/851; H10W72/874; H10W72/884; H10W90/701; H10W90/731; H10W90/732; H10W90/751; H10W90/753; H10W90/754; H10W90/755
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
242 words
A multichip module comprising: a multichip module substrate; a first chip, the first chip having opposed base and bonding faces, the base face being adhered to the multichip module substrate, the first chip bonding face including a central area and a plurality of bonding pads laterally peripheral to the central area; a second chip, the second chip having opposed base and bonding faces, the second chip bonding face including a central area and a plurality of peripheral bonding pads; an adhesive layer interposed between and connecting the first chip bonding face and the second chip base face, the adhesive layer having a thickness and a lateral perimeter, the lateral perimeter being positioned entirely within the central area inside of the peripheral bonding pads; a plurality of first loop bonding wires bonded to and between the respective first chip bonding pads and the multichip module substrate, the respective first loop bonding wires having outwardly projecting loops of a defined loop height, the loop height being defined by the distance between the first chip bonding face and the vertexes of the outwardly projecting loops of the first loop bonding wires, the thickness of the adhesive layer being greater than the loop height to displace the second chip base face in a non-contacting relationship above and with respect to the first wires; and a plurality of second loop bonding wires bonded to and between the respective second chip bonding pads and the multichip module substrate.
Claim 2
Dependent Claim
242 words
A multichip module comprising: a multichip module substrate; a first chip, the first chip having opposed base and bonding faces, the base face being adhered to the multichip module substrate, the first chip bonding face including a central area and a plurality of bonding pads laterally peripheral to the central area; a second chip, the second chip having opposed base and bonding faces, the second chip bonding face including a central area and a plurality of peripheral bonding pads; an adhesive layer interposed between and connecting the first chip bonding face and the second chip base face, the adhesive layer having a thickness and a lateral perimeter, the lateral perimeter being positioned entirely within the central area inside of the peripheral bonding pads; a plurality of first loop bonding wires bonded to and between the respective first chip bonding pads and the multichip module substrate, the respective first loop bonding wires having outwardly projecting loops of a defined loop height, the loop height being defined by the distance between the first chip bonding face and the vertexes of the outwardly projecting loops of the first loop bonding wires, the thickness of the adhesive layer being greater than the loop height to displace the second chip base face in a non-contacting relationship above and with respect to the first wires; and a plurality of second loop bonding wires bonded to and between the respective second chip bonding pads and the multichip module substrate.
Claim 3
Dependent Claim
12 words
The multichip module of claim 1 wherein the adhesive comprises a tape.
Claim 4
Dependent Claim
16 words
The multichip module of claim 1 wherein the adhesive comprises a tape coated with thermoplastic material.
Claim 5
Dependent Claim
93 words
The multichip module of claim 1 wherein the first chip, adhesive and second chip comprise a z-direction multichip stack, the multichip stack having a top-most chip, the top-most chip having a bonding face including a central area and a plurality of bonding pads laterally peripheral to the central area, the multichip module further comprising: an overlying adhesive layer adhered to the top-most chip bonding face, the overlying adhesive layer having a lateral perimeter, the lateral perimeter being positioned entirely within the top chip central area inside of the peripheral top chip bonding pads.
Claim 6
Dependent Claim
103 words
The multichip module of claim 1 wherein the first chip, adhesive and second chip comprise a z-direction multichip stack, the multichip stack having a top-most chip, the top-most chip having a bonding face including a central area and a plurality of bonding pads laterally peripheral to the central area, the multichip module further comprising: an overlying adhesive layer adhered to the top-most chip bonding face, the overlying adhesive layer having a lateral perimeter, the lateral perimeter being positioned entirely within the top chip central area inside of the peripheral top chip bonding pads; and the adhesive and the overlying adhesive comprising a tape.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-20 | 1997-12-20 | 1998-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-20 | 2001-12-20 | 2002-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-20 | 2005-12-20 | 2006-06-21 | $7700.00 | Window Closed / Lapsed |