US5323036A
Expired / Lapsed
US
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Power FET with gate segments covering drain regions disposed in a hexagonal pattern
Assignee: Fairchild Semiconductor Corp
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Filing: 1992-01-21
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Granted: 1994-06-21
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Expires: 2012-01-21
Abstract
Abstract In a power FET composed of a substrate having upper and lower surfaces, the FET providing a current flow path between the upper and lower surfaces, and the FET having a plurality of drain regions extending to the substrate upper surface and an insulated gate electrode disposed on the upper surface, the improvement wherein said drain regions are disposed in a hexagonal lattice pattern, and said gate electrode comprises: a plurality of gate segments each covering a respective drain region; and a plurality of connecting segments each connecting together three of said gate segments.
Inventors
- 👤 John M. S. Neilson
- 👤 Frederick P. Jones
- 👤 Joseph A. Yedinak
- 👤 Christopher L. Rexer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:02
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D62/127; H10D12/00; H10D12/411; H10D12/441; H10D62/17; H10D62/393; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/519
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
152 words
In a power FET composed of a substrate having upper and lower surfaces, the FET providing a current flow path between the upper and lower surfaces, and the FET having a plurality of drain regions extending to the substrate upper surface and an insulated gate electrode disposed on the upper surface, the improvement wherein said drain regions are isolated from one another at said substrate upper surface and are disposed on a hexagonal lattice pattern formed of a plurality of regular hexagons, with each hexagon having six straight sides and each drain region being positioned on a respective straight side, and said gate electrode comprises: a plurality of gate segments disposed in a hexagonal lattice pattern which coincides with the hexagonal lattice pattern in which said drain regions are disposed, each gate segment covering a respective drain region; and a plurality of connecting segments each connecting together three of said gate segments.
Claim 2
Dependent Claim
152 words
In a power FET composed of a substrate having upper and lower surfaces, the FET providing a current flow path between the upper and lower surfaces, and the FET having a plurality of drain regions extending to the substrate upper surface and an insulated gate electrode disposed on the upper surface, the improvement wherein said drain regions are isolated from one another at said substrate upper surface and are disposed on a hexagonal lattice pattern formed of a plurality of regular hexagons, with each hexagon having six straight sides and each drain region being positioned on a respective straight side, and said gate electrode comprises: a plurality of gate segments disposed in a hexagonal lattice pattern which coincides with the hexagonal lattice pattern in which said drain regions are disposed, each gate segment covering a respective drain region; and a plurality of connecting segments each connecting together three of said gate segments.
Claim 3
Dependent Claim
30 words
A power FET as defined in claim 1 wherein each said drain region has a center which coincides substantially with the midpoint of a respective straight side of a hexagon.
Claim 4
Dependent Claim
21 words
A power FET as defined in claim 2 wherein said gate segments and said connecting segments lie in a common plane.
Claim 5
Dependent Claim
19 words
A power FET as defined in claim 3 wherein each said connecting segment has the form of a Y.
Claim 6
Dependent Claim
17 words
A power FET as defined in claim 4 wherein each said gate segment has a circular shape.
Claim 7
Dependent Claim
19 words
A power FET as defined in claim 2 wherein each said connecting segment has the form of a Y.
Claim 8
Dependent Claim
17 words
A power FET as defined in claim 6 wherein each said gate segment has a circular shape.
Claim 9
Dependent Claim
21 words
A power FET as defined in claim 1 wherein said gate segments and said connecting segments lie in a common plane.
Claim 10
Dependent Claim
19 words
A power FET as defined in claim 8 wherein each said connecting segment has the form of a Y.
Claim 11
Dependent Claim
17 words
A power FET as defined in claim 9 wherein each said gate segment has a circular shape.
Claim 12
Dependent Claim
19 words
A power FET as defined in claim 1 wherein each said connecting segment has the form of a Y.
Claim 13
Dependent Claim
17 words
A power FET as defined in claim 11 wherein each said gate segment has a circular shape.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-20 | 1997-12-20 | 1998-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-20 | 2001-12-20 | 2002-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-20 | 2005-12-20 | 2006-06-21 | $7700.00 | Window Closed / Lapsed |