Semiconductor memory device being coupled by auxiliary power lines to a main power line

Claim 2

A semiconductor memory device comprising a plurality of memory cell arrays in which a potential difference between a pair of bit lines to which memory cells of the arrays are coupled is detected and amplified by a sense amplifier operating responsive to a sense latch signal on a common node, and the memory cells of the arrays are coupled via a power supply line to an output of an internal power supply generating circuit, the internal power supply generating circuit coupled to a power supply pad for connection with an external power supply and for causing a voltage drop, in which: said power supply line comprises a main line disposed along the plurality of memory cell arrays and a plurality of auxiliary lines, each auxiliary line disposed within each respective memory cell array, the main line having a line resistance; and said main line and each said auxiliary line disposed within each respective memory cell array are coupled to each other via a respective resistive element corresponding to each respective memory cell array, each respective resistive element having a resistance greater than the line resistance of the main line from the power supply to a memory cell array located farthest from the power supply.

Claim 3

A semiconductor memory device, comprising: first, second and third nodes; a power supply for supplying a first potential; an internal power supply generating circuit, coupled to the power supply, for providing a second potential to the first node, the second potential being less than the first potential; a power supply line coupled to the first, second and third nodes, the second node being coupled to the power supply line between where the first and the third nodes are each coupled to the power supply line, the power supply line having a resistance between the first node and the third node; a first memory cell block including a first common node, a first memory cell for storing data therein, a first sensing amplifier coupled to the first memory cell through a pair of first bit lines for amplifying a difference potential between each bit line of the first pair of bit lines; a second memory cell block including a second common node, a second memory cell for storing data therein, a second sensing amplifier coupled to the second memory cell through a pair of second bit lines for amplifying a difference potential between each bit line of the second pair of bit lines; a first resistance element, coupled between the second node and the first common node, having a resistance greater than the resistance of the power supply line; and a second resistance element coupled between the third node and the second common node, having a resistance substantially equal to the resistance of the first resistance element.

Claim 4

A semiconductor memory device, comprising: first, second and third nodes; a power supply for supplying a first potential; an internal power supply generating circuit, coupled to the power supply, for providing a second potential to the first node, the second potential being less than the first potential; a power supply line coupled to the first, second and third nodes, the second node being coupled to the power supply line between where the first and the third nodes are each coupled to the power supply line, the power supply line having a resistance between the first node and the third node; a first memory cell block including a first common node, a first memory cell for storing data therein, a first sensing amplifier coupled to the first memory cell through a pair of first bit lines for amplifying a difference potential between each bit line of the first pair of bit lines; a second memory cell block including a second common node, a second memory cell for storing data therein, a second sensing amplifier coupled to the second memory cell through a pair of second bit lines for amplifying a difference potential between each bit line of the second pair of bit lines; a first resistance element, coupled between the second node and the first common node, having a resistance greater than the resistance of the power supply line; and a second resistance element coupled between the third node and the second common node, having a resistance substantially equal to the resistance of the first resistance element.

Claim 5

A semiconductor memory device comprising: a plurality of memory cell arrays, each memory cell array including a plurality of memory cells arranged in rows, each respective row of memory cells coupled to a respective pair of bit lines, each respective pair of bit lines coupled to a corresponding sense amplifier, each respective sense amplifier coupled to a first power supply node through a power supply line, each sense amplifier responsive to a respective sense latch signal for detecting and amplifying a potential difference between bit lines of the pair of bit lines coupled to the sense amplifier, the plurality of memory cell arrays arranged to form a row of memory cell arrays; the power supply line including, a main line arranged along the row formed by the plurality of memory cell arrays, a plurality of auxiliary lines, each respective auxiliary line arranged within each respective memory cell array; and a respective resistive element coupled between each auxiliary line and the main line at respective locations along the main line, wherein, the main line includes a first line resistance between the first power supply node and a first location where a resistive element is coupled to the main power line and a second line resistance between each subsequent location where a resistive element is coupled to the main line, each respective resistive element coupled to the main line having a resistance such that the resistance of the respective resistive element plus the first line resistance of the main line the second line resistance between the location where the respective resistive element is coupled to the main line and the first location equals a predetermined value of resistance.

Claim 6

A semiconductor memory device comprising: a plurality of memory cell arrays, each memory cell array including a plurality of memory cells arranged in rows, each respective row of memory cells coupled to a respective pair of bit lines, each respective pair of bit lines coupled to a corresponding sense amplifier, each respective sense amplifier coupled to a first power supply node through a power supply line, each sense amplifier responsive to a respective sense latch signal for detecting and amplifying a potential difference between bit lines of the pair of bit lines coupled to the sense amplifier, the plurality of memory cell arrays arranged to form a row of memory cell arrays; the power supply line including, a main line arranged along the row formed by the plurality of memory cell arrays, a plurality of auxiliary lines, each respective auxiliary line arranged within each respective memory cell array; and a respective resistive element coupled between each auxiliary line and the main line at respective locations along the main line, wherein, the main line includes a first line resistance between the first power supply node and a first location where a resistive element is coupled to the main power line and a second line resistance between each subsequent location where a resistive element is coupled to the main line, each respective resistive element coupled to the main line having a resistance such that the resistance of the respective resistive element plus the first line resistance of the main line the second line resistance between the location where the respective resistive element is coupled to the main line and the first location equals a predetermined value of resistance.

Claim 7

The semiconductor memory device according to claim 3, further comprising an internal power supply generating circuit coupled between the first power supply node and a external power supply for causing a voltage drop.