EP0175880A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1985-07-29
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Granted: —
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Expires: 2005-07-29
Abstract
Abstract A first transistor (59) is connected between each of data sensing means and V DD power source. A second transistor (60) is connected between each of data sensing means and ground. A control signal to control the active state of each data sensing means (50) is directly applied to the gate of the first transistor. The control signal is applied to the gate of the second transistor, with a time delay corresponding to that by a word line (32). The timing of rendering each data sensing means active in state is substantially coincident with the optimum timing of a potential change on each corresponding bit line (12, 14).
Inventors
- 👤 Junichi C/O Patent Division Miyamoto
- 👤 Jun-Ichi C/O Patent Division Tsujimoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 15:51
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/14; G11C5/00; G11C5/06; G11C5/063; G11C5/14; G11C7/00; G11C7/06; G11C7/065
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
139 words
A semiconductor memory device comprising: a plurality of bit line pairs (12, 14), each pair of bit lines being respectively connected to a memory cell and a dummy cell which are respectively selected by signals derived from word lines; a plurality of means (50) for sensing data by amplifying a potential difference between each pair of bit lines; a plurality of first transistors (59, 60) connected between said data sensing means and a power source for receiving at the gates, with an extremely small time delay, control signals to control the active state of each of said data sensing means; and a plurality of second transistors (58, 61) connected between said data sensing means and the power source respectively connected in series to said first transistors, and for receiving at the gates said control signals with predetermined time delays.
Claim 2
Dependent Claim
139 words
A semiconductor memory device comprising: a plurality of bit line pairs (12, 14), each pair of bit lines being respectively connected to a memory cell and a dummy cell which are respectively selected by signals derived from word lines; a plurality of means (50) for sensing data by amplifying a potential difference between each pair of bit lines; a plurality of first transistors (59, 60) connected between said data sensing means and a power source for receiving at the gates, with an extremely small time delay, control signals to control the active state of each of said data sensing means; and a plurality of second transistors (58, 61) connected between said data sensing means and the power source respectively connected in series to said first transistors, and for receiving at the gates said control signals with predetermined time delays.
Claim 3
Dependent Claim
53 words
A semiconductor memory device according to claim 1, characterized in that said time delay of said control signal applied to the gate of each of said second transistors is substantially equal to the time delay of a signal on the word line connected to the memory cell associated with said data sensing means.
Claim 4
Dependent Claim
34 words
A semiconductor memory device according to claim 1, characterized in that the gate capacitance of each of said second transistors is substantially equal to that of the memory cell connected to said word line.
Claim 5
Dependent Claim
38 words
A semiconductor memory device according to claim 1, characterized in that said first transistors are each arranged closer to said power source, and said second transistors are shared in use by a plurality of said data sensing means.
Claim 6
Dependent Claim
21 words
A semiconductor memory device according to claim 1, characterized in that each of said data sensing means includes a flip-flop circuit.
References Cited (Backward Citations)
No citation records indexed.
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