Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
138 words
An integrated memory circuit, comprising an external and an internal power supply junction point and a voltage converter which is connected between said junction points in order to apply a voltage to the internal power supply point which is lower than the voltage applied to the external power supply junction point, the memory circuit comprising a matrix of memory cells which are arranged in rows an columns and which are connected to the internal supply voltage, each of said rows of memory cells being connected to a word line, each memory cell in a column being connected to a bit line via an access transistor, characterized in that before each read cycle the lowest bit line voltage equals the internal supply voltage minus a threshold voltage of the access transistor connecting the memory cell to the bit line.
Claim 2
Dependent Claim
138 words
An integrated memory circuit, comprising an external and an internal power supply junction point and a voltage converter which is connected between said junction points in order to apply a voltage to the internal power supply point which is lower than the voltage applied to the external power supply junction point, the memory circuit comprising a matrix of memory cells which are arranged in rows an columns and which are connected to the internal supply voltage, each of said rows of memory cells being connected to a word line, each memory cell in a column being connected to a bit line via an access transistor, characterized in that before each read cycle the lowest bit line voltage equals the internal supply voltage minus a threshold voltage of the access transistor connecting the memory cell to the bit line.
Claim 3
Dependent Claim
28 words
An integrated memory circuit as claimed in Claim 1, characterized in that the maximum potential of the control signal on the word lines equals the external supply voltage.
Claim 4
Dependent Claim
59 words
An integrated memory circuit as claimed in Claim 1 or 2, characterized in that the transistors which are controlled by a column selection circuit for selectively connecting a bit line and a non-bit line to a local read bus are controlled by means of selection signals whose maximum voltage equals the voltage applied to the external power supply point.
Claim 5
Dependent Claim
146 words
An integrated memory circuit as claimed in Claim 1, 2 or 3, characterized in that the integrated memory circuit comprises a circuit for generating a second internal supply voltage which comprises a control transistor whose gate is connected to the internal supply voltage terminal and whose source is connected to a junction point which carries the second supply voltage and whereto there is also connected a discharge transistor whose gate is connected to a control output of a voltage controller, a first and a second input of which are connected to the internal supply voltage point and the junction point between the control transistor and the discharge transistor, respectively, the voltage controller rendering the discharge transistor conductive if the voltage difference between the internal supply voltage terminal and said junction point is substantially smaller than the threshold voltage of the access transistor of the memory cells.
Claim 6
Dependent Claim
49 words
An integrated memory circuit as claimed in Claim 4, characterized in that a transistor, being connected as a load, and a capacitance are connected parallel to the discharge transistor, the capacitance value of the capacitance being substantially larger than that of the parasitic capacitance of a bit line pair.
Claim 7
Dependent Claim
52 words
An integrated memory circuit as claimed in Claim 5, characterized in that a series connection of a further load transistor and a transistor switch are connected parallel to the discharge transistor, which transistor switch is switched on by a switch enable signal on the chip enable input of the integrated memory circuit.