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JPS60140586A Expired / Lapsed JP ⏱️ 0.0 years remaining

Memory circuit

Assignee: NEC Corp
•
Filing: 1983-12-28
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Granted: —
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Expires: 2003-12-28
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Abstract

Abstract PURPOSE:To allow variance of operation speed and power consumption on the user side by controlling variably operation speed and power consumption in accordance with the control signal level which impresses the control terminal. CONSTITUTION:A speed/electric power means 2 consists of depression-type MOS transistors Q1, Q2,...QN whose drain is connected to a power source Vcc, the gate is connected to a control terminal 1 in common, and the source is connected to circuit blocks CB1, CB2,...CBN which constitute a memory circuit. Electric power supply to each circuit block is executed from the power source Vcc through respective MOS transistors. When ''on'' resistance of the transistors Q1,...QN changes in accordance with the signal level of a control signal PC, and the signal level of a control signal CP becomes higher, ''on'' resistance lowers, power consumption increases, and operation speed becomes faster. Since operation speed and power consumption change, the memory circuit can set the value freely.

Inventors

  • 👤 Yasuo Akatsuka
  • 👤 赤塚 泰生

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 18:31
CPC Classifications
G; G11; G11C; G11C7/00

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