Semiconductor memory having a dynamic discharge circuit

Claim 1

A semiconductor memory comprising memory cells which are arranged in a matrix of rows and columns, each memory cell comprising two emitter-connected transistors whose collectors are cross-wise connected to the bases, the memory cells in a matrix row being connected parallel to one another between a first and a second power supply line, switching means being connected to the first power supply line in order to bring the first power supply line to a line selection potential or to a rest potential, a current source being connected to the second power supply line in order to sustain data stored in each memory cell connected to said line, said switching means comprising a first transistor which is connected to the first power supply line by way of its emitter and whose base receives voltage pulses in order to bring the first power supply line to the line selection potential and also comprising a further transistor for the discharging of the first power supply line from the line selection potential to the rest potential or for the discharging of the second power supply line, said memory also comprising detection means for detecting the end of a voltage pulse on the base of the first transistor and for controlling the further transistor, said detection means being at least indirectly connected to the base of the first transistor for this purpose, characterized in that the detection means comprise a second transistor whose emitter is connected to the first power supply line and whose base is at least indirectly connected to the base of the first transistor, the further transistor being controlled via the collector of the second transistor, the first and the second transistor being of a first and a second conductivity type, respectively.