US4295210A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power supply system for monolithic cells
Assignee: International Business Machines Corp
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Filing: 1979-09-04
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Granted: 1981-10-13
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Expires: 1999-09-04
Abstract
Abstract A power-supply system for use in a monolithic memory characterized in that the power dissipation of the memory is reduced. Each word line is connected to a current switch circuit comprised of a first transistor the collector of which is connected to a voltage V1, its base being connected to the output of the address decoder, a second transistor the collector of which is connected to a voltage V2. V3 being the second voltage impressed on the memory cells (where |V2| is larger in magnitude than |V1| and |V3| is larger in magnitude than |V2|). The emitters are connected to each other and to the corresponding word line. According to the state of the decoder output, the first or the second transistor is conducting, whereby the selected cells are subjected to a voltage having a magnitude of |V3-V1| and the non-selected cells are subjected to a voltage having a magnitude of |V3-V2|.
Inventors
- 👤 Herve Beranger
- 👤 Claude Marzin
- 👤 Dominique M. Omet
- 👤 Jean-Luc Peter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:34
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/415; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/22; G11C11/411; G11C11/4116
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
201 words
In a monolithic memory having n word lines and an address decoder having n outputs, said monolithic memory being characterized by an improved bilevel powering system, said powering system including: n discrete current switch circuit means; each of said n current switch circuit means having an input and an output; each of said n current switch circuit means having its input connected to a predetermined one of said n outputs of said address decoder and its output connected to a discrete one of said n word lines; and each said current switch circuit means including, a first transistor having an emitter, base and collector and a second transistor having an emitter, base and collector, said base of said first transistor being connected to said input of said current switch circuit means, said collector of said first transistor being connected to a source of potential having a magnitude |V1|, said base of said second transistor being connected to a reference potential, said collector of said second transistor being connected to a source of potential having at magnitude of |V2|, where |V1|<|V2|, and said emitters of said first and second transistors being connected in common to the output of said current switch means.
Claim 2
Dependent Claim
201 words
In a monolithic memory having n word lines and an address decoder having n outputs, said monolithic memory being characterized by an improved bilevel powering system, said powering system including: n discrete current switch circuit means; each of said n current switch circuit means having an input and an output; each of said n current switch circuit means having its input connected to a predetermined one of said n outputs of said address decoder and its output connected to a discrete one of said n word lines; and each said current switch circuit means including, a first transistor having an emitter, base and collector and a second transistor having an emitter, base and collector, said base of said first transistor being connected to said input of said current switch circuit means, said collector of said first transistor being connected to a source of potential having a magnitude |V1|, said base of said second transistor being connected to a reference potential, said collector of said second transistor being connected to a source of potential having at magnitude of |V2|, where |V1|<|V2|, and said emitters of said first and second transistors being connected in common to the output of said current switch means.
Claim 3
Dependent Claim
169 words
In a monolithic memory, said monolithic memory including an array of memory cells, said array having n columns and m rows of memory cells; n pairs of bit lines, each pair of said n pairs of bit lines being connected to a discrete one of said n columns of memory cells; m pairs of word lines, each pair of said m pairs of word lines including a first wordline and a second wordline; each of said m rows of memory cells being connected between the first wordline and the second wordline of a discrete pair of said m pairs of wordlines; address decoder means having a multi-bit address input and m discrete outputs; m current switch circuit means, each of said m current switch circuit means being connected between a discrete one of said m outputs of said decoder means and the first wordline of a discrete one of said m pairs of wordlines; each of said second wordlines being connected via circuit means to a potential source |V3|.
Claim 4
Dependent Claim
169 words
In a monolithic memory, said monolithic memory including an array of memory cells, said array having n columns and m rows of memory cells; n pairs of bit lines, each pair of said n pairs of bit lines being connected to a discrete one of said n columns of memory cells; m pairs of word lines, each pair of said m pairs of word lines including a first wordline and a second wordline; each of said m rows of memory cells being connected between the first wordline and the second wordline of a discrete pair of said m pairs of wordlines; address decoder means having a multi-bit address input and m discrete outputs; m current switch circuit means, each of said m current switch circuit means being connected between a discrete one of said m outputs of said decoder means and the first wordline of a discrete one of said m pairs of wordlines; each of said second wordlines being connected via circuit means to a potential source |V3|.
Claim 5
Dependent Claim
123 words
In a monolithic memory as claimed in claim 2 wherein each of said current switch circuit means includes: a first transistor having an emitter, base and collector and a second transistor having an emitter, base and collector; said base of said first transistor being connected to a discrete one of m outputs of said decoder means; said collector of said first transistor being connected to a potential source |V1|; said base of said second transistor being connected to a reference potential; said collector of said second transistor being connected to a potential source |V2|, where |V1|<|V2|<|V3|; and said emitters of said first and second transistors being connected in common to the second wordline of a discrete one of said m pairs of wordlines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-12 | 1985-04-13 | 1985-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-12 | 1989-04-13 | 1989-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-12 | 1993-04-13 | 1993-10-13 | $7700.00 | Window Closed / Lapsed |