Patent US5313111A successfully refreshed from Google Patents.
US5313111A
Expired / Lapsed
US
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Substrate slew circuit providing reduced electron injection
Assignee: Texas Instruments Inc
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Filing: 1993-08-11
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Granted: 1994-05-17
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Expires: 2013-08-11
Abstract
Abstract The described embodiments of the present invention provide a substrate slew circuit that eliminates electron injection. The slew circuit comprises a semiconductor substrate, first and second transistors and a control circuit. One of a source/drain of the source/drain of the first transistor is connected to a reference voltage. One of a source/drain of the second transistor is connected to a gate of the first transistor, the other of the source/drain of the second transistor is coupled to receive a first voltage signal from a substrate pump. The control circuit is connected to the gate of the second transistor for controlling the passage of current from the other of the source/drain of the second transistor to the one of a source/drain of the second transistor.
Inventors
- 👤 Darryl Walker
- 👤 Daniel F. McLaughlin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 15:10
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205; H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; H03; H03K; H03K17/00; H03K17/08; H03K17/081; H03K17/0812; H03K17/08122
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
102 words
A device, comprising: a semiconductor substrate; one of a source/drain of a first transistor connected to said substrate, the other of a source/drain of said first transistor directly connected to a DC voltage; one of a source/drain of a second transistor directly connected to a gate of said first transistor, the other of a source/drain of said second transistor coupled to receive an AC signal; and a circuit connected to the gate of said second transistor for controlling the passage of current from said other of said source/drain of said second transistor to said one of a source/drain of said second transistor.
Claim 2
Independent Claim
102 words
A device, comprising: a semiconductor substrate; one of a source/drain of a first transistor connected to said substrate, the other of a source/drain of said first transistor directly connected to a DC voltage; one of a source/drain of a second transistor directly connected to a gate of said first transistor, the other of a source/drain of said second transistor coupled to receive an AC signal; and a circuit connected to the gate of said second transistor for controlling the passage of current from said other of said source/drain of said second transistor to said one of a source/drain of said second transistor.
Claim 3
Dependent Claim
14 words
The device of claim 1 in which said AC signal is a clock signal.
Claim 4
Dependent Claim
14 words
The device of claim 1 in which said first transistor is an NMOS transistor.
Claim 5
Dependent Claim
14 words
The device of claim 1 in which said second transistor is a PMOS transistor.
Claim 6
Independent Claim
269 words
A device comprising: a) a semiconductor substrate; b) one of a source/drain of a first transistor connected to said substrate, the other of a source/drain of said first transistor connected to a substantially constant reference voltage; c) one of a source/drain of a second transistor connected to a gate of said first transistor, the other of a source/drain of said second transistor coupled to receive a first voltage signal; and d) a circuit connected to the gate of said second transistor for controlling the passage of current from said other of said source/drain of said second transistor to said one of a source/drain of said second transistor, said circuit comprising: (i) a delay circuit having an input coupled to receive a first clock signal and a logic gate having a first input coupled to receive said first clock signal, a second input of said logic gate coupled to an output of said delay circuit and an output coupled to an input of an inverter, an output of said inverter coupled to a first plate of a capacitive element and a second plate of said capacitive element coupled to said gate of said second transistor; and (ii) one of a source/drain of a third transistor rand one of a source/drain of a fourth transistor coupled to receive said first voltage signal, a gate of said third transistor connected to said substrate and a gate of said fourth transistor coupled to receive a second voltage signal, the other of said source/drain of said third transistor and the other source/drain of said fourth transistor coupled to said gate of said second transistor.
Claim 7
Independent Claim
269 words
A device comprising: a) a semiconductor substrate; b) one of a source/drain of a first transistor connected to said substrate, the other of a source/drain of said first transistor connected to a substantially constant reference voltage; c) one of a source/drain of a second transistor connected to a gate of said first transistor, the other of a source/drain of said second transistor coupled to receive a first voltage signal; and d) a circuit connected to the gate of said second transistor for controlling the passage of current from said other of said source/drain of said second transistor to said one of a source/drain of said second transistor, said circuit comprising: (i) a delay circuit having an input coupled to receive a first clock signal and a logic gate having a first input coupled to receive said first clock signal, a second input of said logic gate coupled to an output of said delay circuit and an output coupled to an input of an inverter, an output of said inverter coupled to a first plate of a capacitive element and a second plate of said capacitive element coupled to said gate of said second transistor; and (ii) one of a source/drain of a third transistor rand one of a source/drain of a fourth transistor coupled to receive said first voltage signal, a gate of said third transistor connected to said substrate and a gate of said fourth transistor coupled to receive a second voltage signal, the other of said source/drain of said third transistor and the other source/drain of said fourth transistor coupled to said gate of said second transistor.
Claim 8
Dependent Claim
14 words
The device of claim 5 in which said logic gate is a NOR gate.
Claim 9
Dependent Claim
14 words
The device of claim 5 in which said third transistor is a PMOS transistor.
Claim 10
Dependent Claim
14 words
The device of claim 5 in which said fourth transistor is a PMOS transistor.
Claim 11
Dependent Claim
31 words
The device of claim 5 in which said capacitive element is a PMOS transistor with the source and drain coupled as said first plate and said gate being said second plate.
Claim 12
Dependent Claim
26 words
The device of claim 5 in which said first voltage signal and said second voltage signal are generated by a source outside of the substrate pump.
Claim 13
Independent Claim
77 words
A device, comprising: a semiconductor substrate; one of source/drain of a first transistor connected to said substrate, the other of a source/drain of said first transistor directly connected to a DC voltage; and a first terminal of a second transistor directly connected to a gate of said first transistor, a second terminal of said second transistor coupled to receive a controlled AC signal, an a third terminal of said second transistor connected to a voltage generating circuit.
Claim 14
Independent Claim
77 words
A device, comprising: a semiconductor substrate; one of source/drain of a first transistor connected to said substrate, the other of a source/drain of said first transistor directly connected to a DC voltage; and a first terminal of a second transistor directly connected to a gate of said first transistor, a second terminal of said second transistor coupled to receive a controlled AC signal, an a third terminal of said second transistor connected to a voltage generating circuit.
Claim 15
Dependent Claim
23 words
The device of claim 11 in which said first terminal of sad second transistor is one of a source/drain of said second transistor.
Claim 16
Dependent Claim
14 words
The device of claim 11 in which said AC signal is a clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-16 | 1997-11-15 | 1998-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-16 | 2001-11-15 | 2002-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-16 | 2005-11-15 | 2006-05-17 | $7700.00 | Window Closed / Lapsed |