US4686388A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit substrate bias selection circuit
Assignee: Pitney Bowes Inc
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Filing: 1985-03-12
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Granted: 1987-08-11
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Expires: 2005-03-12
Abstract
Abstract A circuit for selecting one of a plurality of positive voltages when both can be applied to an integrated circuit. The circuit comprises a sensing apparatus for determining which of the plurality of voltages is the highest, apparatus for providing the highest voltage to the substrate and apparatus for applying the highest of the plurality of voltages to the substrate to insure protection and proper operation of the integrated circuit.
Inventors
- 👤 Warren G. Hafner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 22:52
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
107 words
In an integrated circuit including a substrate connected thereto, a substrate bias selection circuit, the substrate bias selection circuit comprising: means for providing a first and second voltage and a reference voltage to the integrated circuit, means coupled to the providing means for sensing whether the first or the second voltage applied to the circuit is higher, said sensing means including a first and second MOSFET circuit means, each said first and second MOSFET circuit means a first P-channel MOSFET respectively connected in parallel with a registor, and means coupled to the sensing means for applying the higher of the first or second voltages to the substrate.
Claim 2
Dependent Claim
107 words
In an integrated circuit including a substrate connected thereto, a substrate bias selection circuit, the substrate bias selection circuit comprising: means for providing a first and second voltage and a reference voltage to the integrated circuit, means coupled to the providing means for sensing whether the first or the second voltage applied to the circuit is higher, said sensing means including a first and second MOSFET circuit means, each said first and second MOSFET circuit means a first P-channel MOSFET respectively connected in parallel with a registor, and means coupled to the sensing means for applying the higher of the first or second voltages to the substrate.
Claim 3
Dependent Claim
26 words
The bias selection circuit of claim 1 in which the sensing circuit further includes an inverter means coupled to the first and second MOSFET circuit means.
Claim 4
Dependent Claim
103 words
In an integrated circuit including substrate connected thereto, a substrate bias selection circuit, the substrate bias selection circuit comprising: means for providing a plurality of voltages including a reference voltage to the integrated circuit, means coupled to the providing means for sensing which of plurality of the voltages applied to the circuit is highest, means coupled to the sensing means for applying the highest of the plurality of voltages to the substrate, said sensing means including a first and second MOSFET circuit means, and the first and second MOSFET circuit means each respectively including a first P-channel MOSFET connected parallel with a resistor.
Claim 5
Dependent Claim
103 words
In an integrated circuit including substrate connected thereto, a substrate bias selection circuit, the substrate bias selection circuit comprising: means for providing a plurality of voltages including a reference voltage to the integrated circuit, means coupled to the providing means for sensing which of plurality of the voltages applied to the circuit is highest, means coupled to the sensing means for applying the highest of the plurality of voltages to the substrate, said sensing means including a first and second MOSFET circuit means, and the first and second MOSFET circuit means each respectively including a first P-channel MOSFET connected parallel with a resistor.
Claim 6
Dependent Claim
26 words
The bias selection circuit of claim 3 in which the sensing circuit further includes an inverter means coupled to the first and second MOSFET circuit means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-10 | 1991-02-09 | 1991-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-10 | 1995-02-09 | 1995-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-10 | 1999-02-09 | 1999-08-11 | $7700.00 | Window Closed / Lapsed |