US4463270A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOS Comparator circuit
Assignee: National Semiconductor Corp
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Filing: 1980-07-24
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Granted: 1984-07-31
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Expires: 2000-07-24
Abstract
Abstract A circuit for detecting a difference in the relative magnitudes of two voltages includes a current sensing circuit connected between the first voltage and ground to thereby cause a first current to flow in the current sensing circuit, an amplifier connected between the second voltage and ground and connected to the current sensing circuit to thereby cause a second current to flow, the second current being equal to the first current when the first voltage is equal to the second voltage, and a variable impedance inverter connected to the first voltage and connected to the amplifier, the variable impedance being controlled by the first voltage, the output of the inverter thereby being related to the difference between the first voltage and the second voltage. The invention is particularly useful for controlling a battery backup power supply in a microprocessor having a volatile memory and for creating precision delay circuits.
Inventors
- 👤 James S. Gordon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:36
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22; H03K5/24; H03K5/2472; G; G01; G01R; G01R19/00; G01R19/0038
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
145 words
A comparator circuit responsive to a change in the difference between a first voltage level at a first terminal and a second voltage level at a second voltage terminal comprising: a current sensing circuit connected between the first voltage terminal and a reference voltage terminal to thereby cause a first current to flow; an amplifier connected between the second voltage terminal, the reference voltage terminal and the current sensing circuit to thereby cause a second current to flow in the amplifier, the second current having a known relationship to the first current when the first voltage level is equal to the second voltage level; and a first inverter having a variable impedance connected to the first voltage level and the amplifier, said variable impedance being controlled by the magnitude of said first voltage level relative to said second voltage level for providing a control signal.
Claim 2
Dependent Claim
145 words
A comparator circuit responsive to a change in the difference between a first voltage level at a first terminal and a second voltage level at a second voltage terminal comprising: a current sensing circuit connected between the first voltage terminal and a reference voltage terminal to thereby cause a first current to flow; an amplifier connected between the second voltage terminal, the reference voltage terminal and the current sensing circuit to thereby cause a second current to flow in the amplifier, the second current having a known relationship to the first current when the first voltage level is equal to the second voltage level; and a first inverter having a variable impedance connected to the first voltage level and the amplifier, said variable impedance being controlled by the magnitude of said first voltage level relative to said second voltage level for providing a control signal.
Claim 3
Dependent Claim
32 words
A circuit as in claim 1 including a second inverter connected to the first inverter to thereby provide a second inverter output signal inverted with respect to the first inverter output signal.
Claim 4
Dependent Claim
56 words
A circuit as in claim 1 wherein the current sensing circuit comprises a first transistor having a drain connected to the first voltage terminal and a second transistor having the source connected to the reference voltage terminal, the source and gate of the first transistor being connected to the drain and gate of the second transistor.
Claim 5
Dependent Claim
70 words
A circuit as in claim 3 wherein the amplifier comprises: a third transistor having a source connected to the reference voltage terminal and a fourth transistor having a drain connected to the second voltage terminal, and the drain of the third transistor is connected to the gate and the source of the fourth transistor; and the gate of the third transistor is connected to the gate of the second transistor.
Claim 6
Dependent Claim
88 words
A circuit as in claim 4 wherein the first inverter comprises: a fifth transistor having a source connected to the reference voltage terminal, and a sixth transistor having a drain connected to the second voltage terminal, and the drain of the fifth transistor is connected to the source of the sixth transistor to provide the first inverter output signal; the gate of the fifth transistor is connected to the drain of the third transistor; and the gate of the sixth transistor is connected to the first voltage terminal.
Claim 7
Dependent Claim
77 words
A circuit as in claim 2 wherein the second inverter comprises: a first transistor having a source connected to the reference voltage terminal and a second transistor having a drain connected to the second voltage terminal, and the drain of the first transistor is connected to the gate and source of the second transistor to provide the second inverter output signal; and the gate of the first transistor is connected to receive the first inverter output signal.
Claim 8
Dependent Claim
29 words
A circuit as in claim 2 wherein the second inverter output signal is connected to a switching transistor to switchably connect the second voltage level to said desired circuit.
Claim 9
Dependent Claim
16 words
A circuit as in claim 4 wherein the first transistor and the fourth transistor are matched.
Claim 10
Dependent Claim
17 words
A circuit as in claim 8 wherein the first and fourth transistors are depletion mode MOS transistors.
Claim 11
Dependent Claim
15 words
The apparatus of claim 5 wherein said sixth transistor is a depletion mode MOS transistor.
Claim 12
Dependent Claim
15 words
The apparatus of claim 6 wherein said second transistor is a depletion mode MOS transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-31 | 1988-01-30 | 1988-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-31 | 1992-01-30 | 1992-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-31 | 1996-01-30 | 1996-07-31 | $7700.00 | Window Closed / Lapsed |