High performance static latches with complete single event upset immunity

Claim 2

A bi-stable asymmetric response latch, consisting essentially of: (a) a first and a second inverter, each of said inverters having a p-channel transistor and a n-channel transistor, said inverters cross-coupled so that a source/drain of said n-channel transistor of said first inverter is cross-coupled to a gate of said p-channel transistor of said second inverter at a first coupling node, and a source/drain of said p-channel transistor of said second inverter is cross-coupled to a gate of said n-channel transistor of said first inverter at a second coupling node; wherein one of said inverters has a single hardened logic state and the other of said inverters has a soft logic state; (b) a first voltage dividing means interposed between said p-channel source/drain of said first inverter and said first cross-coupling node wherein the logic state of said first inverter can only be changed by an ion strike when the voltage level at said first coupling node is low; (c) a second voltage dividing means interposed between said second coupling node and a n-channel source/drain of said second inverter wherein the logic state of said second inverter can only be changed by an ion strike when the voltage level at said second coupling node is high.

Claim 3

The bi-stable asymmetric response latch of claim 1 wherein said first and second voltage dividing means are resistors.

Claim 4

The bi-stable asymmetric response latch of claim 1 wherein said p-channel and said n-channel transistors are field effect transistors, and said first and second voltage dividing means are depletion mode transistors.

Claim 5

The bi-stable asymmetric response latch of claim 3 wherein said field effect transistors are enhancement mode MOSFETs, and said depletion mode transistors are MOSFETs.

Claim 6

A logical memory cell, comprising: (a) a first bi-stable asymmetric response latch consisting essentially of a first and a second inverter, each of said inverters having a p-channel transistor and a n-channel transistor, said inverters cross-coupled so that a source/drain of said n-channel transistor of said first inverter is cross-coupled to a gate of said p-channel transistor of said second inverter at a first coupling node, and a source/drain of said p-channel transistor of said second inverter is cross-coupled to a gate of said n-channel transistor of said first inverter at a second coupling node wherein one of said first and second inverters has a single hardened logic state and the other of said first and second inverters has a soft logic state; a first voltage dividing means interposed between said p-channel source/drain of said first inverter and said first cross-coupling node wherein the logic state of said first inverter can only be changed by an ion strike when the voltage level at said first coupling node is low; a second voltage dividing means interposed between said second coupling node and a n-channel transistor of said second inverter wherein the logic state of said second inverter can only be changed by an ion strike when the voltage level at said second coupling node is high; a first bit line connected at a first information node to said first inverter between said first n-channel transistor and said first coupling node; and a second bit line connect at a second information node to said second inverter between said second n-channel transistor and said second voltage dividing means; (b) a second bi-stable asymmetric response latch consisting essentially a third and a fourth inverter, each of said inverters having a p-channel transistor and a n-channel transistor, said inverters cross-coupled so that a source/drain of said n-channel transistor of said third inverter is cross-coupled to a gate of said p-channel transistor of said fourth inverter at a third coupling node, and a source/drain of said p-channel transistor of said fourth inverter is cross-coupled to a gate of said n-channel transistor of said third inverter at a fourth coupling node wherein one of said third and fourth inverters has a single hardened logic state and the other of said third and fourth inverters has a soft logic state; a third voltage dividing means interposed between said p-channel source/drain of said third inverter and said third cross-coupling node wherein the logic state of said third inverter can only be changed by an ion strike when the voltage level at said third coupling node is low; a fourth voltage dividing means interposed between said fourth coupling node and a n-channel transistor of said fourth inverter wherein the logic state of said fourth inverter can only be changed by an ion strike when the voltage level at said fourth coupling node is high; a third bit line connected at a third information node to said third inverter between said third n-channel transistor and said third coupling node; and a fourth bit line connected at a fourth information node to said fourth inverter between said fourth n-channel transistor and said fourth voltage dividing means; (c) a first sensing means connected between said first and second bit lines to detect the state of said first and second information nodes; (d) a second sensing means connected between said third and forth bit lines to detect the state of said third and fourth information nodes; (e) an AND gate connected to receive outputs of said first and second sensing means to compare data on said first and second sensing means.

Claim 7

A logical memory cell, comprising: (a) a first bi-stable asymmetric response latch consisting essentially of a first and a second inverter, each of said inverters having a p-channel transistor and a n-channel transistor, said inverters cross-coupled so that a source/drain of said n-channel transistor of said first inverter is cross-coupled to a gate of said p-channel transistor of said second inverter at a first coupling node, and a source/drain of said p-channel transistor of said second inverter is cross-coupled to a gate of said n-channel transistor of said first inverter at a second coupling node wherein one of said first and second inverters has a single hardened logic state and the other of said first and second inverters has a soft logic state; a first voltage dividing means interposed between said p-channel source/drain of said first inverter and said first cross-coupling node wherein the logic state of said first inverter can only be changed by an ion strike when the voltage level at said first coupling node is low; a second voltage dividing means interposed between said second coupling node and a n-channel transistor of said second inverter wherein the logic state of said second inverter can only be changed by an ion strike when the voltage level at said second coupling node is high; a first bit line connected at a first information node to said first inverter between said first n-channel transistor and said first coupling node; and a second bit line connect at a second information node to said second inverter between said second n-channel transistor and said second voltage dividing means; (b) a second bi-stable asymmetric response latch consisting essentially a third and a fourth inverter, each of said inverters having a p-channel transistor and a n-channel transistor, said inverters cross-coupled so that a source/drain of said n-channel transistor of said third inverter is cross-coupled to a gate of said p-channel transistor of said fourth inverter at a third coupling node, and a source/drain of said p-channel transistor of said fourth inverter is cross-coupled to a gate of said n-channel transistor of said third inverter at a fourth coupling node wherein one of said third and fourth inverters has a single hardened logic state and the other of said third and fourth inverters has a soft logic state; a third voltage dividing means interposed between said p-channel source/drain of said third inverter and said third cross-coupling node wherein the logic state of said third inverter can only be changed by an ion strike when the voltage level at said third coupling node is low; a fourth voltage dividing means interposed between said fourth coupling node and a n-channel transistor of said fourth inverter wherein the logic state of said fourth inverter can only be changed by an ion strike when the voltage level at said fourth coupling node is high; a third bit line connected at a third information node to said third inverter between said third n-channel transistor and said third coupling node; and a fourth bit line connected at a fourth information node to said fourth inverter between said fourth n-channel transistor and said fourth voltage dividing means; (c) a first sensing means connected between said first and second bit lines to detect the state of said first and second information nodes; (d) a second sensing means connected between said third and forth bit lines to detect the state of said third and fourth information nodes; (e) an AND gate connected to receive outputs of said first and second sensing means to compare data on said first and second sensing means.

Claim 8

The logical memory cell of claim 5 wherein said p-channel and said n-channel transistors are field effect transistors, and said first and second voltage dividing means are resistors.

Claim 9

The logical memory cell of claim 5 wherein said p-channel and said n-channel transistors are field effect transistors, and said first and second voltage dividing means are depletion mode transistors.

Claim 10

The logical memory cell of claim 7 wherein said field effect transistors are enhancement mode MOSFETs, and said depletion mode transistors are MOSFETs.

Claim 11

A logical memory cell, comprising: (a) a first and second asymmetrical response latch; (b) an information latch, connected in parallel with and interposed between said first and second asymmetrical response latches, said information latch further comprising two transistors which are of the same type as, and are parallel to, transistors connected to an information node; (c) a plurality of bit lines connected to said information latch to provide data input control; (d) access transistors connected to said information latch on a plurality of output lines; wherein said control latches protect logical information hardened into said information latch.

Claim 12

A logical memory cell, comprising: (a) a first and second asymmetrical response latch; (b) an information latch, connected in parallel with and interposed between said first and second asymmetrical response latches, said information latch further comprising two transistors which are of the same type as, and are parallel to, transistors connected to an information node; (c) a plurality of bit lines connected to said information latch to provide data input control; (d) access transistors connected to said information latch on a plurality of output lines; wherein said control latches protect logical information hardened into said information latch.