US4969125A — Asynchronous segmented precharge architecture

Claim 1

Independent Claim 236 words

An improved memory having enhanced power dissipation, enhanced radiation hardness, and capable of enhanced static page mode operation, comprising: a row decode means having an input connected to an input address bus, and including an address transition detector, for outputting an ATD signal when the address on the address bus changes, said row decoder having output lines connected to the word lines of a memory array; said memory array being organized into a plurality of segments, each segment having a plurality of columns of storage devices, each column including a pair of bit lines, each bit line in each respective pair being connected to one of a pair of storage nodes for each storage cell in a column; each segment of said plurality of segments in said array containing a precharge means which includes an equalization circuit connected to each pair of bit lines in each respective column in the segment, for precharging and equalizing the bit lines in the segment when the segment is not being accessed; control means having an input connected to said address transition detection means and a control output coupled to each equalization circuit, for momentarily enabling the equalization circuit for each accessed segment in said array, when said ATD signal signifies a row address change; segments not being accessed are thereby capable of reinstating balance potentials on respective bit line pairs which have incurred discharge due to ionizing radiation effects.

Claim 2

Dependent Claim 236 words

An improved memory having enhanced power dissipation, enhanced radiation hardness, and capable of enhanced static page mode operation, comprising: a row decode means having an input connected to an input address bus, and including an address transition detector, for outputting an ATD signal when the address on the address bus changes, said row decoder having output lines connected to the word lines of a memory array; said memory array being organized into a plurality of segments, each segment having a plurality of columns of storage devices, each column including a pair of bit lines, each bit line in each respective pair being connected to one of a pair of storage nodes for each storage cell in a column; each segment of said plurality of segments in said array containing a precharge means which includes an equalization circuit connected to each pair of bit lines in each respective column in the segment, for precharging and equalizing the bit lines in the segment when the segment is not being accessed; control means having an input connected to said address transition detection means and a control output coupled to each equalization circuit, for momentarily enabling the equalization circuit for each accessed segment in said array, when said ATD signal signifies a row address change; segments not being accessed are thereby capable of reinstating balance potentials on respective bit line pairs which have incurred discharge due to ionizing radiation effects.

Claim 3

Dependent Claim 260 words

An improved memory array having row address inputs connected to a row address decoder and column address inputs connected to a column address decoder, the row address decoder and column address decoder having an address bus connected thereto, the memory being organized into an array having word lines organized into rows and columns having a pair of bit lines for each column, the improvement comprising: said array being segmented into a plurality of segments, each segment containing a portion of all of said bit lines; a bit equalization circuit for each said segment, for precharging and equalizing the potential on each bit line in a bit line pair, when activated; a precharge and equalization circuit control means, having an input coupled to said input address lines, and an output coupled to a precharge and equalization circuit in each respective segment of said array, for enabling said precharge and equalization circuits on those segments of the array which are not selected by said input address and for disabling the precharge and equalization circuits on that segment of the array which is selected by the input address; said bit line pairs in segments not selected by said input address being maintained at a substantially equal voltage so that when one of said bit lines in a bit line pair in a segment not selected by said input address suffers a discharge due to an ionizing radiation effect, said activated precharge and equalization circuit on the non-selected segment will equalize the potential thereof; whereby the radiation immunity of the memory array is improved.

Claim 4

Dependent Claim 260 words

An improved memory array having row address inputs connected to a row address decoder and column address inputs connected to a column address decoder, the row address decoder and column address decoder having an address bus connected thereto, the memory being organized into an array having word lines organized into rows and columns having a pair of bit lines for each column, the improvement comprising: said array being segmented into a plurality of segments, each segment containing a portion of all of said bit lines; a bit equalization circuit for each said segment, for precharging and equalizing the potential on each bit line in a bit line pair, when activated; a precharge and equalization circuit control means, having an input coupled to said input address lines, and an output coupled to a precharge and equalization circuit in each respective segment of said array, for enabling said precharge and equalization circuits on those segments of the array which are not selected by said input address and for disabling the precharge and equalization circuits on that segment of the array which is selected by the input address; said bit line pairs in segments not selected by said input address being maintained at a substantially equal voltage so that when one of said bit lines in a bit line pair in a segment not selected by said input address suffers a discharge due to an ionizing radiation effect, said activated precharge and equalization circuit on the non-selected segment will equalize the potential thereof; whereby the radiation immunity of the memory array is improved.

Claim 5

Dependent Claim 50 words

The memory array of claim 2 which further comprises: said precharge and equalization circuits including precharging means for precharging both bit lines in a bit line pair to a potential less than the supply of voltage for the memory; whereby the power dissipation required for precharging said lines is minimized.

Claim 6

Dependent Claim 79 words

The memory array of claim 2 wherein: said bit line pairs in segments not selected by said input address of said array have substantially equal potentials and are precharged thereby enabling the immediate selection of storage elements in said non-selected segments following the accessing of storage elements in a segment of the array which is selected by the input address, without the necessity of engaging in a precharge cycle; whereby high speed static paging operations can be carried out.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1993-11-05	1994-05-07	1994-11-06	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1997-11-05	1998-05-07	1998-11-06	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2001-11-05	2002-05-07	2002-11-06	$7700.00	Window Closed / Lapsed

Asynchronous segmented precharge architecture

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