Driving circuit for a shared sense amplifier

Claim 2

A driving circuit for a shared sense amplifier which drives at a high speed a shared sense amplifier circuit including two pairs of it lines (3 R , 4 R and 3 L , 4 L ) respectivey connected with memory cells (MC 1R , MC NR and MC 1L , MC NL ), a sense amplifier (1, 2) provided between said two pairs of bit lines for amplifying information read from said memory cells, a first transfer transistor group (7 R , 8 R or 7 L , 8 L ) interposed between one of said pairs of bit lines (3 R , 4 R or 3 L , 4 L ) and said sense amplifier and a secnd transfer transistor group (7 L , 8 L or 7 R , 8 R ) interposed between the other pair of bit lines (3 L , 4 L or 3 R , 4 R ) and said sense amplifier (1, 2) thereby to share said sense amplifier by said two pairs of bit lines (3 R , 4 R and 3 L , 4 L ), said driving circuit comprising: a clamp clock generation circuit for generating a clamp clock (φ 5 ) respondig at a high speed to addressing of said memory cells; a decoder for decoding said clamp clock (φ 5 ); and on-off control means for controlling on-off operations of said first and second transfer transistor groups on the basis of an output from said decoder, said on-off control means including clamp means for clamping, upon addressing of any one of said memory calls, the gate voltage of said transfer transistor group interposed between the pair of bit lines not connected with said addressed memory cell and said sense amplifier, said gate voltage equal to the precharge voltage of said bit lines thereby to turn off said transfer transistor group.

Claim 3

A driving circuit for a shared sense amplifier in accordance with claim 1, wherein said on-off control means includes means for setting, in a standby state before said addressing of said memory cells, the gate voltage levels of respective transfer transistor groups to be higher than a respectie total of precharge voltage levels of said bit lines and threshold voltage levels of said transfer transistor groups thereby to turn on said respective transfer transistor groups.

Claim 4

A driving circuit for a shared sense amplifier in accordance with claim 1, wherein said two pairs of bit lines are formed by folded bit lines (3 R , 4 R and 3 L , 4 L ) respectively.

Claim 5

A driving circuit for a shared sense amplifier in accordance with claim 1, wherein said two pairs of bit lines are formed by open bit lines respectively.

Claim 6

A driving circuit for a shared sense apmplifier in accordance with claim 1, wherein said clamp clock generation circuit includes: a first potential level source (V cc ), a second potential level (ground) source having a potential level different from that of said first potential level source, a first transistor (M 6 ) having a first conducting terminal connected with said first potential level source, a second transistor (M 8 ) interposed between a second conducting terminal of said first transistor and said second potential level source, first circuit means (M 1 -M 4 ) for making said first transistor conductive and said second transistor non-conductive in response to said addressing of said memory cell, boostsing capacitor means (C 6 ) inerposed between said second conducting terminal of said first transistor and the gate terminal of said first transistor for making said first transistor conductive at a high speed, and second circuit means (M 9 ) for producing said clamp clock (φ 5 ) on the basis of change in potential at said second conducting terminal of said first transistor.

Claim 7

A driving circuit for a shared sense amplifier in accordance with claim 1, wherein said on-off control means includes first transistor means connected to the precharge voltage of said bit lines and responsive to a precharge clock signal for said bit lines, further transistor means responsive to clock signals for activating and deactivating the sense amplifier, and output transistor means responsive to said further transistor means and to said first transitor means for outputting a control clock signal for controlling operations of said first and second transfer transistor groups.

Claim 8

A driving circuit for a shared sense amplifier in accordance with claim 6, wherein said output transistor means comprises a pair of parallel connected transistors having gates connected to outputs of said first transistor means, a first of said pair of output transistors connected to said clamp clock signal and operable or responding to initiation of said clamp clock signal to clamp the transfer transistor groups for the nonselected bit lines to said precharge voltage level, thereby to turn off said transfer transistor group, a second of said pair of putput transistors connected to said clock signals for said sense amplifier and operable in response to said clock signals for sais sense amplifier to continue to clamp said transfer transistor group to said precharge voltagae after termination of said clamp clock signal.

Claim 9

A driving circuit for a shares sense amplifier in accordance with claim 7, wherein said further transistor means is connected to receive a delayed invereted form of said clock signal for said sense amplifier and operable in response thereto for providing to said output transistors a gate signal for turning off said output transistors.

Claim 10

A driving circuit for a shared sense amplifier in accordance with claim 8, further comprising means responsive to a level raising clock signal for providing to the gates of said transfer transistor group a voltage level for turning on said transfer transistor group subsequent to turning off of said output transistors.

Claim 11

In a driving circuit for a shared sense amplifier which drives at a high speed a shared sense amplifier circuit including two pairs of bit lines (3 R , 4 R and 3 L , 4 L ) respectively connected with memory cells (MC 1R , MC NR and MC 1L , MC NL ), a sense amplifier (1, 2) provided between said two pairs of bit lines for amplifying information read from said memory cells, a first transfer transistor group (7 R , 8 R or 7 L , 8 L ) interposed between one of said pairs of bit lines (3 R , 4 R or 3 L , 4 L ) and said sense amplifier and a second transfer transistor group (7 L , 8 L or 7 R , 8 R ) interposed between the other pair of bit lines (3 L , 4 L or 3 R , 4 R ) and said sense amplifier (1, 2) thereby to share said sense amplifier by said two pairs of bit lines (3 R , 4 R and 3 L , 4 L ), the improvemet comprising: on-off control means for controlling on-off operations of said first and second transfeer transistor groups based on an output from a decoder for decoding a clamp clock signal, said on-off control means including clamp means, operable upon addressing of one of said memory cells, connected to said sense amplifier by one pair of bit lines, for disconnecting from the sense amplifier the other pair of bit lines connected between a non-addressed memory cell and the sense amplifier, said claiming means operable for disconnecting the other pair of bit lines by clamping the gate voltage of the transfer transistor group connecting the other pair of bit lines to the sense amplifier too the precharge voltage level for the bit lines.