US5134581A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Highly stable semiconductor memory with a small memory cell area
Assignee: Micron Memory Japan Ltd
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Filing: 1990-10-29
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Granted: 1992-07-28
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Expires: 2010-10-29
Abstract
Abstract In order to obtain a highly stable SRAM cell having a small cell area, a cell ratio R is set to be R=(W DEFF /L DEFF )/(W TEFF /L TEFF )<3 where L DEFF and W DEFF denote an effective channel length and an effective channel width of two driver MOSFETs 3 and 4 respectively, and L TEFF and W TEFF denote an effective channel length and an effective channel width of two transfer MOSFETs 5 and 6 respectively. Further, a maximum current I R flowing into the active loads MOSFETs 1 and 2 is set to be greater than a current I L (1×10 -8 A) that flows into the driver MOSFET 5 when a threshold voltage is applied across the gate and the cource of the MOSFET 5. The pair of active load MOSFETs 1 and 2 are stacked on the driver MOSFETs 3 and 4 and on the transfer MOSFETs 5 and 6.
Inventors
- 👤 Koichiro Ishibashi
- 👤 Katsuro Sasaki
- 👤 Katsuhiro Shimohigashi
- 👤 Toshiaki Yamanaka
- 👤 Naotaka Hashimoto
- 👤 Takashi Hashimoto
- 👤 Akihiro Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:35
CPC Classifications
H; H10; H10B; H10B10/00; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/413; G11C11/417; G11C11/419; H10B10/12; H10B10/125
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
136 words
A semiconductor memory in which static memory cells each comprised of two driver MOSFETs and two transfer MOSFETs of a first conductivity type are formed on a semiconductor substrate, wherein two FETs of a second conductivity type are formed as active loads of said memory cells and overlie at least one of the driver and transfer MOSFETs, wherein a condition (W DEFF /L DEFF )/(W TEFF / L TEFF )<3 is established in which L DEFF and W DEFF denote an effective channel length and an effective channel width of said two driver MOSFETs, respectively, and L TEFF and W TEFF denote an effective channel length and an effective channel width of said two transfer MOSFETs, respectively, and wherein a current flowing into the active load FETs is set to be greater than 1×10 -8 A.
Claim 2
Dependent Claim
136 words
A semiconductor memory in which static memory cells each comprised of two driver MOSFETs and two transfer MOSFETs of a first conductivity type are formed on a semiconductor substrate, wherein two FETs of a second conductivity type are formed as active loads of said memory cells and overlie at least one of the driver and transfer MOSFETs, wherein a condition (W DEFF /L DEFF )/(W TEFF / L TEFF )<3 is established in which L DEFF and W DEFF denote an effective channel length and an effective channel width of said two driver MOSFETs, respectively, and L TEFF and W TEFF denote an effective channel length and an effective channel width of said two transfer MOSFETs, respectively, and wherein a current flowing into the active load FETs is set to be greater than 1×10 -8 A.
Claim 3
Dependent Claim
19 words
A semiconductor memory according to claim 1, wherein the active load FETs consist of polysilicon thin film transistors (TFTs).
Claim 4
Dependent Claim
85 words
A semiconductor memory according to claim 2, wherein a condition, t WD <t cycle , is established where t WD denotes the width of a voltage pulse on a word line that renders said two transfer MOSFETs conductive and t cycle denotes the minimum cycle time of the semiconductor memory, in order to provide a time during which said two transfer MOSFETs become nonconductive, and one node in said memory cell is electrically charged by said current of said polysilicon TFTs during said nonconductive time.
Claim 5
Dependent Claim
29 words
A semiconductor memory according to claim 2, wherein the channel direction of said two transfer MOSFETs is substantially in parallel with the channel direction of said two drive MOSFETs.
Claim 6
Dependent Claim
29 words
A semiconductor memory according to claim 3, wherein the channel direction of said two transfer MOSFETs is substantially in parallel with the channel direction of said two driver MOSFETs.
Claim 7
Dependent Claim
26 words
A semiconductor memory according to claim 5, wherein the driver and transfer MOSFETs are n-channel conductivity type and said active load FETs are p-channel conductivity type.
Claim 8
Dependent Claim
26 words
A semiconductor memory according to claim 1, wherein the driver and transfer MOSFETs are n-channel conductivity type and said active load FETs are p-channel conductivity type.
Claim 9
Dependent Claim
26 words
A semiconductor memory according to claim 2, wherein the driver and transfer MOSFETs are n-channel conductivity type and said active load FETs are p-channel conductivity type.
Claim 10
Dependent Claim
200 words
A semiconductor memory of high stability in which static memory cells each comprised of two driver MOSFETs and two transfer MOSFETs of a first conductivity type are formed in a principal surface region of a semiconductor substrate, each driver MOSFET having a drain and gate cross-coupled to the gate and drain of the other driver MOSFET and said two transfer MOSFETs having individual channels coupled between a corresponding one of a pair of complementary bit lines and the drain of a driver MOSFET, respectively, wherein two FETs of a second conductivity type are formed above the principal surface region of said semiconductor substrate as active loads of said memory cell and which overlie at least one of the driver and transfer MOSFETs, wherein a condition (W DEFF /L DEFF )/(W TEFF /L TEFF )<3 is established in which L DEFF and W DEFF denote an effective channel length and an effective channel width of said two driver MOSFETs, respectively, and L TEFF and W TEFF denote an effective channel length and an effective channel width of said two transfer MOSFETs, respectively, and wherein a current flowing into the active load FETs is set to be greater than 1×10 -8 A.
Claim 11
Dependent Claim
200 words
A semiconductor memory of high stability in which static memory cells each comprised of two driver MOSFETs and two transfer MOSFETs of a first conductivity type are formed in a principal surface region of a semiconductor substrate, each driver MOSFET having a drain and gate cross-coupled to the gate and drain of the other driver MOSFET and said two transfer MOSFETs having individual channels coupled between a corresponding one of a pair of complementary bit lines and the drain of a driver MOSFET, respectively, wherein two FETs of a second conductivity type are formed above the principal surface region of said semiconductor substrate as active loads of said memory cell and which overlie at least one of the driver and transfer MOSFETs, wherein a condition (W DEFF /L DEFF )/(W TEFF /L TEFF )<3 is established in which L DEFF and W DEFF denote an effective channel length and an effective channel width of said two driver MOSFETs, respectively, and L TEFF and W TEFF denote an effective channel length and an effective channel width of said two transfer MOSFETs, respectively, and wherein a current flowing into the active load FETs is set to be greater than 1×10 -8 A.
Claim 12
Dependent Claim
19 words
A semiconductor memory according to claim 9, wherein said active loads FETs consist of polysilicon thin film transistors (TFTs).
Claim 13
Dependent Claim
85 words
A semiconductor memory according to claim 10, wherein a condition, t W <t cycle , is established where t WD denotes the width of a voltage pulse on a word line that renders said two transfer MOSFETs conductive and t cycle denotes the minimum cycle time of the semiconductor memory, in order to provide a time during which said two transfer MOSFETs become nonconductive, and one node in said memory cell is electrically charged by said current of said polysilicon TFTs during said nonconductive time.
Claim 14
Dependent Claim
36 words
A semiconductor memory according to claim 11, wherein said two transfer MOSFETs are disposed so that the direction of the corresponding channels thereof are substantially in parallel with the channel direction of said two driver MOSFETs.
Claim 15
Dependent Claim
26 words
A semiconductor memory according to claim 12, wherein the driver and transfer MOSFETs are n-channel conductive type and said active load FETs are p-channel conductivity type.
Claim 16
Dependent Claim
36 words
A semiconductor memory according to claim 10, wherein said two transfer MOSFETs are disposed so that the direction of the corresponding channels thereof are substantially in parallel with the channel direction of said two driver MOSFETs.
Claim 17
Dependent Claim
26 words
A semiconductor memory according to claim 9, wherein the driver and transfer MOSFETs are n-channel conductivity type and said active load FETs are p-channel conductivity type.
Claim 18
Dependent Claim
26 words
A semiconductor memory according to claim 10, wherein the driver and transfer MOSFETs are n-channel conductivity type and said active load FETs are p-channel conductivity type.
References Cited (Backward Citations)
US4623989A
Cited
US4760561A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-28 | 1996-01-27 | 1996-07-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-28 | 2000-01-27 | 2000-07-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-28 | 2004-01-27 | 2004-07-28 | $7700.00 | Window Closed / Lapsed |