US4914629A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory cell including single event upset rate reduction circuitry
Assignee: Texas Instruments Inc
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Filing: 1988-09-07
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Granted: 1990-04-03
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Expires: 2008-09-07
Abstract
Abstract The rate of single event upset in a memory cell is reduced by a pair of active devices in the cross-coupling between a pair of inverters. The active devices are controlled by voltages internal to the memory cell such that writing into the cell is not slowed significantly.
Inventors
- 👤 Terence G. W. Blake
- 👤 Theodore W. Houston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:17
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/4125; G11C5/00; G11C5/005
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
107 words
A bi-stable logic device comprising: a set of cross-coupled inverters, said set of inverters including first and second inverters; and a pair of transistors connected to the cross-coupling of the inverters so as to provide a time delay in effecting voltage changes at selected nodes within the cell via an impedance path through said pair of transistors which lies between said selected nodes, the gate of a first transistor of said pair being connected to a first source/drain of a second transistor of said pair in addition to the gate of a second transistor of said pair being connected to a first source/drain of said first transistor.
Claim 2
Dependent Claim
107 words
A bi-stable logic device comprising: a set of cross-coupled inverters, said set of inverters including first and second inverters; and a pair of transistors connected to the cross-coupling of the inverters so as to provide a time delay in effecting voltage changes at selected nodes within the cell via an impedance path through said pair of transistors which lies between said selected nodes, the gate of a first transistor of said pair being connected to a first source/drain of a second transistor of said pair in addition to the gate of a second transistor of said pair being connected to a first source/drain of said first transistor.
Claim 3
Dependent Claim
50 words
A bi-stable logic device as recited in claim 1 wherein a second source/drain of said first transistor of said pair is connected to the input of said first inverter and wherein said first source/drain of said first transistor of said pair is connected to the output of said second inverter.
Claim 4
Dependent Claim
50 words
A bi-stable logic device as recited in claim 2 wherein said second source/drain of said second transistor of said pair is connected to said input of said second inverter and wherein said first source/drain of said second transistor of said pair is connected to said output of said first inverter.
Claim 5
Dependent Claim
50 words
A bi-stable logic device as recited in claim 1 wherein a second source/drain of said first transistor of said pair is connected to the output of said first inverter and wherein said first source/drain of said first transistor of said pair is connected to the input of said second inverter.
Claim 6
Dependent Claim
47 words
A bi-stable logic device as recited in claim 4 wherein a second source/drain of said second transistor is connected to said output of said second inverter and wherein said first source/drain of said second transistor of said pair is connected to said input of said first inverter.
Claim 7
Dependent Claim
19 words
A bi-stable logic device as recited in claim 1 wherein said field effect transistors are metal oxide semiconductor transistors.
Claim 8
Dependent Claim
21 words
A bi stable logic device as recited in claim 1 wherein each inverter includes a p-channel transistor and a n-channel transistor.
References Cited (Backward Citations)
US4725981A
Cited
US4797804A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-02 | 1993-10-02 | 1994-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-02 | 1997-10-02 | 1998-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-02 | 2001-10-02 | 2002-04-03 | $7700.00 | Window Closed / Lapsed |