US5301282A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Controlling bus allocation using arbitration hold
Assignee: International Business Machines Corp
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Filing: 1991-10-15
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Granted: 1994-04-05
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Expires: 2011-10-15
Abstract
Abstract An arbiter with an arbitration hold feature is provided which makes it possible to begin an arbitration cycle while information is still being transferred via a bus because the arbiter does not reallocate the bus until the present transfer is complete, as indicated by the arbitration hold feature. Accordingly, arbitration can essentially be overlapped with transfer of information over the bus, thus increasing the amount of information which can be transferred in a given interval of time.
Inventors
- 👤 Nader Amini
- 👤 Bechara F. Boury
- 👤 Terence J. Lohman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 03:18
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/30; G06F13/36; G06F13/362
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
189 words
An information handling system comprising a processor, a memory, a bus, said bus electrically connectable to a controller device, said processor and said memory to allow information transfers via said bus between the controller device, said processor and said memory, the controller device and the processor being capable of controlling information transfers via said bus, and means for selectively generating an arbitration hold signal, said arbitration hold signal indicating not to reallocate said bus, a central arbiter, said central arbiter controlling allocation of said bus such that one of the controller device and the processor become a present controller device, the present controller device controlling a present information transfer via said bus, said central arbiter receiving said arbitration hold signal indicating to said arbiter that the present information transfer is occurring and not to reallocate said bus, said central arbiter using said arbitration hold signal to allow the controller device and said processor to arbitrate for said bus while the present information transfer is occurring, said central arbiter granting access to said bus when said arbitration hold signal indicates that said central arbiter can reallocate said bus as needed.
Claim 2
Dependent Claim
189 words
An information handling system comprising a processor, a memory, a bus, said bus electrically connectable to a controller device, said processor and said memory to allow information transfers via said bus between the controller device, said processor and said memory, the controller device and the processor being capable of controlling information transfers via said bus, and means for selectively generating an arbitration hold signal, said arbitration hold signal indicating not to reallocate said bus, a central arbiter, said central arbiter controlling allocation of said bus such that one of the controller device and the processor become a present controller device, the present controller device controlling a present information transfer via said bus, said central arbiter receiving said arbitration hold signal indicating to said arbiter that the present information transfer is occurring and not to reallocate said bus, said central arbiter using said arbitration hold signal to allow the controller device and said processor to arbitrate for said bus while the present information transfer is occurring, said central arbiter granting access to said bus when said arbitration hold signal indicates that said central arbiter can reallocate said bus as needed.
Claim 3
Dependent Claim
27 words
The apparatus of claim 1 wherein said central arbiter includes a central arbiter state machine for receiving said arbitration hold signal and controlling reallocation of said bus.
Claim 4
Dependent Claim
85 words
The apparatus of claim 2 wherein said central arbiter state machine includes a masked arbitration portion, an unmasked arbitration portion and a grant portion, said masked arbitration portion includes a masked arbitration idle state and said unmasked arbitration portion includes an unmasked arbitration idle state, and said arbitration hold signal forcing said central arbiter state machine to one of said masked arbitration idle state and said unmasked arbitration idle state when receiving an active arbitration hold signal and said present controller device releases said bus.
Claim 5
Dependent Claim
51 words
The apparatus of claim 3 wherein said masked arbitration portion includes a masked refresh state, said masked refresh state controlling a masked refresh function for said memory, and upon completing said masked refresh function, said masked refresh state transitioning to said masked idle state when said arbitration hold signal is active.
Claim 6
Dependent Claim
51 words
The apparatus of claim 4 wherein said unmasked arbitration portion includes an unmasked refresh state, said unmasked refresh state controlling an unmasked refresh function for said memory, and upon completing said unmasked refresh function said unmasked refresh state transitioning to said masked idle state when said arbitration hold signal is active.
Claim 7
Dependent Claim
63 words
The apparatus of claim 4 wherein said grant portion includes a bus grant state, said bus grant state allowing said present controller device to transfer information via said bus, and upon said bus grant state relinquishing ownership of said bus, said grant state transitioning to one of said masked idle state and said unmasked idle state when said arbitration hold signal is active.
Claim 8
Dependent Claim
96 words
The apparatus of claim 4 further comprising: a direct memory access (DMA) controller for controlling DMA transfer and wherein said grant portion includes a direct memory access grant state, said direct memory access grant state granting said direct memory access controller ownership of said bus to transfer information via said bus, and said unmasked arbitration portion includes a DMA arbitration state, said DMA arbitration state allowing said DMA controller to complete a DMA transfer while allowing arbitration to occur, and upon entering said DMA arbitration state, arbitration is locked until said arbitration hold signal goes inactive.
Claim 9
Dependent Claim
71 words
The apparatus of claim 2 wherein said central arbiter state machine includes an idle state, said arbitration hold signal forcing said central arbiter state machine to said idle state when receiving an active arbitration hold signal, and said idle state using said arbitration hold signal to allow the controller device and said processor to arbitrate for said bus while information from said present controller device is still transferring via said bus.
Claim 10
Dependent Claim
23 words
The apparatus of claim 8 wherein said central arbiter state machine remains in said idle state until said arbitration hold signal goes inactive.
Claim 11
Dependent Claim
27 words
The apparatus of claim 8 wherein said central arbiter state machine includes an arbitration portion and a grant portion, and said arbitration portion includes said idle state.
Claim 12
Dependent Claim
44 words
The apparatus of claim 10 wherein said arbitration portion includes a refresh state, said fresh state controlling a refresh function for said memory, and upon completing said refresh function, said refresh state transitioning to said idle state when said arbitration hold signal is active.
Claim 13
Dependent Claim
54 words
The apparatus of claim 10 wherein said grant portion includes a bus grant state, said bus grant state allowing said controller device to transfer information via said bus, and upon said bus grant state relinquishing ownership of said bus, said grant state transitioning to said idle state when said arbitration hold signal is active.
Claim 14
Dependent Claim
96 words
The apparatus of claim 10 further comprising: a direct memory access controller for controlling direct memory access transfers and wherein said grant portion includes a direct memory access grant state, said direct memory access grant state granting said direct memory access controller ownership of said bus to transfer information via said bus, and said arbitration portion includes a DMA arbitration state, said DMA arbitration state allowing said DMA controller to complete a DMA transfer while allowing arbitration to occur, and upon entering said DMA arbitration state, arbitration is locked until said arbitration hold signal goes inactive.
Claim 15
Independent Claim
201 words
An apparatus for controlling allocation of a bus in an information handling system, the information handling system including a processor, a memory, and the bus, the bus electrically connecting the processor and the memory to allow information transfers between the processor and the memory, the bus being electrically connectable to a controller device to allow the controller device to transfer information via the bus, the controller device and the processor being capable of controlling transfers of information via the bus, the apparatus comprising: a central arbiter, said central arbiter controlling allocation of the bus such that one of the controller device and the processor become a present controller device, the present controller device controlling a present information transfer via the bus, and said central arbiter receiving an arbitration hold signal indicating to said arbiter not to reallocate said bus, said arbitration hold signal being selectively provided by a means for generating said arbitration hold signal, said arbiter using said arbitration hold signal to allow the controller device and the processor to arbitrate for the bus while the present information transfer is occurring, said arbiter granting access to said bus when said hold signal indicates that central arbiter can reallocate said bus.
Claim 16
Independent Claim
201 words
An apparatus for controlling allocation of a bus in an information handling system, the information handling system including a processor, a memory, and the bus, the bus electrically connecting the processor and the memory to allow information transfers between the processor and the memory, the bus being electrically connectable to a controller device to allow the controller device to transfer information via the bus, the controller device and the processor being capable of controlling transfers of information via the bus, the apparatus comprising: a central arbiter, said central arbiter controlling allocation of the bus such that one of the controller device and the processor become a present controller device, the present controller device controlling a present information transfer via the bus, and said central arbiter receiving an arbitration hold signal indicating to said arbiter not to reallocate said bus, said arbitration hold signal being selectively provided by a means for generating said arbitration hold signal, said arbiter using said arbitration hold signal to allow the controller device and the processor to arbitrate for the bus while the present information transfer is occurring, said arbiter granting access to said bus when said hold signal indicates that central arbiter can reallocate said bus.
Claim 17
Dependent Claim
27 words
The apparatus of claim 14 wherein said central arbiter includes a central arbiter state machine for receiving said arbitration hold signal and controlling reallocation of the bus.
Claim 18
Dependent Claim
86 words
The apparatus of claim 15 wherein said central arbiter state machine includes a masked arbitration portion, an unmasked arbitration portion and a grant portion, said masked arbitration portion includes a masked arbitration idle state and said unmasked arbitration portion includes an unmasked arbitration idle state, and said arbitration hold signal forcing said central arbiter state machine to said one of said masked arbitration idle state and said unmasked arbitration idle state when receiving an active arbitration hold signal and said present controller device releasing said bus.
Claim 19
Dependent Claim
51 words
The apparatus of claim 16 wherein said masked arbitration portion includes a masked refresh state, said masked refresh state controlling a masked refresh function for said memory, and upon completing said masked refresh function, said masked refresh state transitioning to said masked idle state when said arbitration hold signal is active.
Claim 20
Dependent Claim
51 words
The apparatus of claim 17 wherein said unmasked arbitration portion includes an unmasked refresh state, said unmasked refresh state controlling an unmasked refresh function for said memory, and upon completing said unmasked refresh function, said unmasked refresh state transitioning to said masked idle state when said arbitration hold signal is active.
Claim 21
Dependent Claim
63 words
The apparatus of claim 16 wherein said grant portion includes a bus grant state, said bus grant state allowing said present controller device to transfer information via said bus, and upon said bus grant state relinquishing ownership of said bus, said grant state transitioning to one of said masked idle state and said unmasked idle state when said arbitration hold signal is active.
Claim 22
Dependent Claim
100 words
The apparatus of claim 16 wherein the information handling system further includes a direct memory access (DMA) controller for controlling DMA transfers, and said grant portion includes a direct memory access grant state, said direct memory access grant state granting said direct memory access controller ownership of said bus to transfer information via said bus, and said unmasked arbitration portion includes a DMA arbitration state, said DMA arbitration state allowing said DMA controller to complete a DMA transfer while allowing arbitration to occur, and upon entering said DMA arbitration state, arbitration is locked until said arbitration hold signal goes inactive.
Claim 23
Dependent Claim
71 words
The apparatus of claim 15 wherein said central arbiter state machine includes an idle state, said arbitration hold signal forcing said central arbiter state machine to said idle state when receiving an active arbitration hold signal, and said idle state using said arbitration hold signal to allow the controller device and said processor to arbitrate for said bus while information from said present controller device is still transferring via said bus.
Claim 24
Dependent Claim
23 words
The apparatus of claim 21 wherein said central arbiter state machine remains in said idle state until said arbitration hold signal goes inactive.
Claim 25
Dependent Claim
27 words
The apparatus of claim 21 wherein said central arbiter state machine includes an arbitration portion and a grant portion, and said arbitration portion includes said idle state.
Claim 26
Dependent Claim
44 words
The apparatus of claim 23 wherein said arbitration portion includes a refresh state, said refresh state controlling a refresh function for said memory, and upon completing said refresh function, said refresh state transitioning to said idle state when said arbitration hold signal is active.
Claim 27
Dependent Claim
54 words
The apparatus of claim 23 wherein said grant portion includes a bus grant state, said bus grant state allowing said controller device to transfer information via said bus, and upon said bus grant state relinquishing ownership of said bus, said grant state transitioning to said idle state when said arbitration hold signal is active.
Claim 28
Dependent Claim
96 words
The apparatus of claim 23 further comprising: a direct memory access controller for controlling direct memory access transfers and wherein said grant portion includes a direct memory access grant state, said direct memory access grant state granting said direct memory access controller ownership of said bus to transfer information via said bus, and said arbitration portion includes a DMA arbitration state, said DMA arbitration state allowing said DMA controller to complete a DMA transfer while allowing arbitration to occur, and upon entering said DMA arbitration state, arbitration is locked until said arbitration hold signal goes inactive.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-04 | 1997-10-04 | 1998-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-04 | 2001-10-04 | 2002-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-04 | 2005-10-04 | 2006-04-05 | $7700.00 | Window Closed / Lapsed |