Bus arbitration logic

Claim 1

In an interactive computer terminal having a bus and various subsystems, accessing said bus according to their assigned priority level, such as a central processor unit (CPU), a direct memory access controller (DMA), a random access memory (RAM), terminal display unit, a keyboard, chip refresh controller, direct memory access channel (DMA), screen refresh controller and keyboard controller communicating with each other via a bus system, each of said subsystems having a priority level which may vary according to their individual states of operation, for accessing said bus, bus arbitration logic for arbitrating access to said bus among the various subsystems comprising: (a) bus decoder means in said bus arbitration logic responsive to first electronic signals indicative of requests from said subsystems in different states of operation which have predetermined priority levels which vary according to the state of operation of the subsystem requesting access to said bus, said decoder for decoding the first electronic signals into second electronic signals; (b) first logic means responsive to said second electronic signals from said bus decoder means for providing third signals for awarding said bus system to one of said subsystems according to a priority level based on the state of operation of said subsystem, and; (c) second logic means responsive to said first logic means for providing fourth signals for awarding access of said bus to said subsystems in accordance to predetermined different priority levels of said subsystems independent of their state of operation.