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EP0382469A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Arbitration of bus access in digital computers

Assignee: Compaq Computer Corp
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Filing: 1990-02-06
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Granted: —
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Expires: 2010-02-06
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Abstract

Abstract A bus arbitration protocol and accompanying bus arbitration logic for multiple-processor computer systems is described in which each processing module (12,12a) has a local cache (16,16a). Several bus arbitration policies are enforced on contending devices which effectively introduce delay states into the arbitration behavior exhibitied by each device. The bus arbitration protocol employs a distributed method of arbitration control involving an essentially fixed prioritization of arbitrating devices.

Inventors

  • 👤 John S. Thayer
  • 👤 Paul R. Culley
  • 👤 Montgomery C. Mcgraw

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-06 05:02
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/368; G06F13/374

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 123 words
A computer system with bus arbitration, comprising: a plurality of devices (12,12a,18) sharing a common bus (24), any one of said devices asserting a request signal on said bus when it requires access to the bus; arbitration circuitry (32) coupled to said bus and detecting any said request signal and asserting an arbitrate signal on said bus to establish an arbitrate condition; each of said devices (12,12a,18) asserting a priority signal in response to said arbitrate signal, and the one of the devices asserting the highest level of priority gaining control of said bus; characterised by: said one of the devices including a timing circuit to prevent it from asserting said request signal for a selected time after completing use of the bus.
Claim 2
Dependent Claim 123 words
A computer system with bus arbitration, comprising: a plurality of devices (12,12a,18) sharing a common bus (24), any one of said devices asserting a request signal on said bus when it requires access to the bus; arbitration circuitry (32) coupled to said bus and detecting any said request signal and asserting an arbitrate signal on said bus to establish an arbitrate condition; each of said devices (12,12a,18) asserting a priority signal in response to said arbitrate signal, and the one of the devices asserting the highest level of priority gaining control of said bus; characterised by: said one of the devices including a timing circuit to prevent it from asserting said request signal for a selected time after completing use of the bus.
Claim 3
Dependent Claim 24 words
A system according to claim 1, including first and second processor devices (12,12a) and a plurality of other devices (18) sharing a common bus.
Claim 4
Dependent Claim 36 words
A system according to claim 1 or claim 2, including means in said one of the devices to prevent it from relinquishing control of the bus for a time period after completing use of the bus.
Claim 5
Independent Claim 42 words
A system according to any of claims 1 to 3, wherein said one of the devices retains control of said bus and prevents said arbitrate condition from being established for a selected time after another of said devices asserts said request signal.
Claim 6
Dependent Claim 23 words
A system according to claim 3 or claim 4, wherein said one of the devices is the first of said processor devices (12,12a).
Claim 7
Independent Claim 215 words
A method for arbitrating for access to a common bus (24) shared by a plurality of devices (12,12a,18) in a computer system, comprising the steps of: detecting a condition wherein a device wants access to said bus, and a condition wherein any device previously having control of said bus has relinquished control; when said conditions have been detected, asserting an arbitrate condition by signalling to all of said devices via said bus; detecting said arbitrate condition at any of said devices wanting use of the bus and asserting a priority code onto said bus by any said devices wanting access to determine which one of said devices is asserting the highest of the priority codes and allowing said one of the devices to assume control of said bus; withdrawing said priority code by any said devices asserting a lower priority code to leave only the highest of the priority codes asserted, and the one of said devices asserting said highest of the priority codes assuming control of said bus; characterised in that when said one of the devices has completed use of said bus, it relinquishes control of the bus and refrains from use of the bus for a preselected period of time, to allow others of said devices to have access to the bus.
Claim 8
Independent Claim 215 words
A method for arbitrating for access to a common bus (24) shared by a plurality of devices (12,12a,18) in a computer system, comprising the steps of: detecting a condition wherein a device wants access to said bus, and a condition wherein any device previously having control of said bus has relinquished control; when said conditions have been detected, asserting an arbitrate condition by signalling to all of said devices via said bus; detecting said arbitrate condition at any of said devices wanting use of the bus and asserting a priority code onto said bus by any said devices wanting access to determine which one of said devices is asserting the highest of the priority codes and allowing said one of the devices to assume control of said bus; withdrawing said priority code by any said devices asserting a lower priority code to leave only the highest of the priority codes asserted, and the one of said devices asserting said highest of the priority codes assuming control of said bus; characterised in that when said one of the devices has completed use of said bus, it relinquishes control of the bus and refrains from use of the bus for a preselected period of time, to allow others of said devices to have access to the bus.
Claim 9
Dependent Claim 27 words
A method according to claim 6, wherein said common bus is shared by first (12) and second (12a) CPU devices and a plurality of other devices (18).
Claim 10
Dependent Claim 19 words
A method according to claim 7, wherein one of said processor devices asserts a higher priority than the other.
Claim 11
Independent Claim 21 words
A method according to any of claims 6 to 8, wherein each one of said devices asserts a different priority code.
Claim 12
Independent Claim 71 words
A method according to any of claims 6 to 9, wherein said one of the devices is a processor device, and said processor device retains control of said bus for a period of time after it has completed use of the bus, before said step of relinquishing control of the bus, to avoid arbitrating for said bus if said one of the devices requires use of the bus during said period.
Claim 13
Dependent Claim 32 words
A method according to claim 10, wherein said one of the devices does not retain control of the bus unless there are no other of said devices requesting use of the bus.
Claim 14
Independent Claim 49 words
A method according to any of claims 6 to 11, wherein any one of said devices may assert a preempt signal on said bus to initiate said arbitrate condition, and wherein a first of said devices will prevent initiation of said arbitrate condition for a selected period of time.
Claim 15
Dependent Claim 15 words
A method according to claim 12, wherein said first of said devices is a CPU.

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