US4977494A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed digital motion controller architecture
Assignee: Palomar Technologies Corp
•
Filing: 1989-02-17
•
Granted: 1990-12-11
•
Expires: 2009-02-17
Abstract
Abstract A system bus (13) carrying multidimensional path data interfaces with a plurality of local microprocessors (24), one for each dimension, through a plurality of dual access memory structures (21), one for each local microprocessor (24). A local arbiter (35) controls access to each dual access memory structure (21), facilitating elimination of wait states in data transfers between the bus (13) and memory (21) and between the local microprocessor (24) and memory (21). The arbiter (35) is implemented using a programmable logic device state machine approach, which implements a mode of operation wherein the circuitry is armed for a transfer between a local microprocessor (24) and the dual access memory (21) and accomplishes such transfer with no wait states. The state machines and dual access memory (21) are driven by a clock which is twice as fast as that driving the local microprocessor (24) and the state machine implementation utilizes this fact to insure memory access to both the system bus (13), and the local microprocessor (24) with priority going to the local microprocessor (24).
Inventors
- 👤 John B. Gabaldon
- 👤 Daniel D. Evans, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 19:21
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/18; G05B19/414; G05B19/4141; G05B2219/00; G05B2219/30; G05B2219/33; G05B2219/33167; G05B2219/33337; G05B2219/34; G05B2219/34042; G05B2219/34076; G05B2219/34205
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
566 words
A digital architecture for a motion controller comprising: a system bus for supplying path data, said path data including a plurality of subsets of path data, each subset corresponding to a desired trajectory of a selected dimension of motion; a plurality of digital processor means, one for each dimension of motion, each processor means for computing a control signal for its dimension of motion utilizing the subset of path data corresponding thereto; a plurality of memory means, each connected to said system bus and to a respective one of said plurality of digital processor means for receiving and storing the corresponding subset of said path data from said bus and for storing data transferred to and from the connected processor; a plurality of control means, one connected to each of said memory means, for receiving control signals from said system bus and from said respective one of said plurality of digital processor means connected to the memory means, for controlling access to the connected memory means in response to said control signals; wherein each said memory means comprises: a random access memory means for storing said corresponding subset of path data; a first gating buffer means responsive to a first buffer gating control signal for gating said subset of path data between said system bus and said random access memory means; and a second gating buffer means responsive to a second buffer gating control signal for gating said subset of path data between said respective one of said digital processor means and said random access memory means; wherein each said control means comprises: means responsive to a first request for access received over said system bus to generate a first access grant control signal and to a second request for access received from said respective one of said digital processor means to generate a second access grant control signal; and sequencer means responsive to said first access grant control signal to generate said first buffer gating control signal and to said second access grant control signal to generate said second buffer gating control signal; wherein said means responsive to a request for access comprises a state machine means for occupying a first state and a second state, said first state being entered in response to a said second request for access, the second state being entered in response to a said first request for access; said architecture further including a first clock means producing a succession of clock edges and wherein said state machine means runs in response to said succession of clock edges and generates said second access grant signal at a first edge of said clock; and wherein said sequencer means enables said second gating buffer means and said random access memory means and causes completion of data transfer between said respective one of said digital processor means and said random access memory means upon occurrence of the next clock edge in said succession after said first clock edge; said architecture further including second clock means for driving said respective one of said digital processor means, the clock rate of said first clock means being selected to be higher than that of said second clock means and such that a data transfer is achieved between said respective one of said digital processor means and said random access memory means before said digital processor means is capable of raising another said second request for access.
Claim 2
Dependent Claim
566 words
A digital architecture for a motion controller comprising: a system bus for supplying path data, said path data including a plurality of subsets of path data, each subset corresponding to a desired trajectory of a selected dimension of motion; a plurality of digital processor means, one for each dimension of motion, each processor means for computing a control signal for its dimension of motion utilizing the subset of path data corresponding thereto; a plurality of memory means, each connected to said system bus and to a respective one of said plurality of digital processor means for receiving and storing the corresponding subset of said path data from said bus and for storing data transferred to and from the connected processor; a plurality of control means, one connected to each of said memory means, for receiving control signals from said system bus and from said respective one of said plurality of digital processor means connected to the memory means, for controlling access to the connected memory means in response to said control signals; wherein each said memory means comprises: a random access memory means for storing said corresponding subset of path data; a first gating buffer means responsive to a first buffer gating control signal for gating said subset of path data between said system bus and said random access memory means; and a second gating buffer means responsive to a second buffer gating control signal for gating said subset of path data between said respective one of said digital processor means and said random access memory means; wherein each said control means comprises: means responsive to a first request for access received over said system bus to generate a first access grant control signal and to a second request for access received from said respective one of said digital processor means to generate a second access grant control signal; and sequencer means responsive to said first access grant control signal to generate said first buffer gating control signal and to said second access grant control signal to generate said second buffer gating control signal; wherein said means responsive to a request for access comprises a state machine means for occupying a first state and a second state, said first state being entered in response to a said second request for access, the second state being entered in response to a said first request for access; said architecture further including a first clock means producing a succession of clock edges and wherein said state machine means runs in response to said succession of clock edges and generates said second access grant signal at a first edge of said clock; and wherein said sequencer means enables said second gating buffer means and said random access memory means and causes completion of data transfer between said respective one of said digital processor means and said random access memory means upon occurrence of the next clock edge in said succession after said first clock edge; said architecture further including second clock means for driving said respective one of said digital processor means, the clock rate of said first clock means being selected to be higher than that of said second clock means and such that a data transfer is achieved between said respective one of said digital processor means and said random access memory means before said digital processor means is capable of raising another said second request for access.
Claim 3
Dependent Claim
59 words
The architecture of claim 1 further including: a trajectory processor means for computing and writing said path data as path data words; and a buffer means for receiving said path data words from said trajectory processor means, for storing said path data words one word at a time, and for outputting said path data words to said system bus.
Claim 4
Dependent Claim
27 words
The architecture of claim 1 wherein said sequencer means sets a plurality of control signals in preparation for occurrence of said first state of said state machine.
Claim 5
Dependent Claim
25 words
The architecture of claim 3 wherein said plurality of control signals comprise said second buffer gating control signal and said second address switch control signal.
Claim 6
Dependent Claim
88 words
The architecture of claim 1 wherein said control signals include first address signals received over said system bus and second address signals generated by the respective one of said digital processor means and wherein said control means further comprises: first switch means for switching said first address signals to said random access memory means in response to a first address switch control signal; and second switch means for switching said second address signals to said random access memory means in response to a second address switch control signal.
Claim 7
Dependent Claim
19 words
The architecture of claim 5 wherein said sequencer means further generates said first and second address switch control signals.
Claim 8
Dependent Claim
55 words
The architecture of claim 6 wherein said sequencer means further generates a first handshaking signal for accomplishing a data transfer between said random access memory means and said system bus and a second handshaking signal for accomplishing a data transfer between said random access memory means and the respective one of said digital processor means.
Claim 9
Dependent Claim
80 words
The architecture of claim 7 wherein said sequencer means further comprises: first programmable logic device means receiving said first access grant control signal and responsive thereto for generating said first buffer gating control signal, said first address switch control signal and said first handshaking signal; and second programmable logic device means receiving said second access grant control signal and responsive thereto for generating said second buffer gating control signal, said second address switch control signal and said second handshaking signal.
Claim 10
Dependent Claim
50 words
The architecture of claim 1 wherein, if said means responsive to a request for access receives a said first request for access and a second request for access simultaneously, said sequencer means delays generation of said first buffer gating control signal and immediately generates said second buffer gating control signal.
Claim 11
Dependent Claim
394 words
Circuitry for transferring path data words between a controller processor means for calculating path data and having an output means for outputting path data words and controller address signals and a local processor means for outputting local processor address signals and generating a control signal for controlling a single dimension of path motion in response to said path data words, said circuitry comprising: a single stage pipeline buffer means having an output and an input connected to the output means of said controller processor means for storing a first path data work output by said processor means while said processor means is calculating a second path data word; a bus means connected to the output of said pipeline buffer means; a random access memory means; a first gating buffer means connected between said bus means and said random access memory means for gating data therebetween in response to a first buffer gating control signal; a second gating buffer means connected between said local processor means and said random access memory means for gating data therebetween in response to a second buffer gating control signal; first switch means for gating addresses from said bus means to said random access memory means in response to a first address gating control signal; second switch means for gating addresses from said local processor means to said random access memory means in response to a second address gating control signal; and control means responsive to said controller address signals and local processor address signals for sequencing generation of said first and second buffer gating control signals and said first and second address gating control signals for controlling data transfers between said controller processor means and said random access memory means and between said local processor means and said random access memory means; wherein said control means includes a state machine means for occupying a null state, a first state, and a second state, said first state being entered in response to receipt of said local processor address signals, the second state being entered in response to receipt of said controller address signals; and wherein, in said null state, said control means produces said second address gating control signal, such that said second switch means is closed during said null state, thereby arming said circuitry for a data transfer between said local processor means and said random access memory means.
Claim 12
Dependent Claim
394 words
Circuitry for transferring path data words between a controller processor means for calculating path data and having an output means for outputting path data words and controller address signals and a local processor means for outputting local processor address signals and generating a control signal for controlling a single dimension of path motion in response to said path data words, said circuitry comprising: a single stage pipeline buffer means having an output and an input connected to the output means of said controller processor means for storing a first path data work output by said processor means while said processor means is calculating a second path data word; a bus means connected to the output of said pipeline buffer means; a random access memory means; a first gating buffer means connected between said bus means and said random access memory means for gating data therebetween in response to a first buffer gating control signal; a second gating buffer means connected between said local processor means and said random access memory means for gating data therebetween in response to a second buffer gating control signal; first switch means for gating addresses from said bus means to said random access memory means in response to a first address gating control signal; second switch means for gating addresses from said local processor means to said random access memory means in response to a second address gating control signal; and control means responsive to said controller address signals and local processor address signals for sequencing generation of said first and second buffer gating control signals and said first and second address gating control signals for controlling data transfers between said controller processor means and said random access memory means and between said local processor means and said random access memory means; wherein said control means includes a state machine means for occupying a null state, a first state, and a second state, said first state being entered in response to receipt of said local processor address signals, the second state being entered in response to receipt of said controller address signals; and wherein, in said null state, said control means produces said second address gating control signal, such that said second switch means is closed during said null state, thereby arming said circuitry for a data transfer between said local processor means and said random access memory means.
Claim 13
Dependent Claim
30 words
The circuitry of claim 10 further including a first clock means producing a succession of clock edges, and wherein said state machine runs in response to said first clock means.
Claim 14
Dependent Claim
39 words
The circuitry of claim 11 wherein said control means causes completion of data transfer between said local processor means and said random access memory means through said second gating buffer means during the period of two said clock edges.
Claim 15
Dependent Claim
73 words
The circuitry of claim 12 further including second clock means for driving said local processor means, the clock rate of said first clock means being selected to be higher than that of said second clock means and such that a data transfer is achieved between said local processor means and said random access memory means before said local processor means is capable of generating a second set of local processor address control signals.
Claim 16
Dependent Claim
135 words
The circuitry of claim 10 wherein said control means further operates said random access memory means at a speed higher than the computational speed of said controller processor means or local processor means such that a data transfer between the local processor means and random access memory means is achieved before the controller processor means can complete computation of a path data word, and wherein said control means further operates such that a data word to be transferred from the controller processor means is stored in the pipeline buffer means while a transfer of data between the local processor means and the random access memory means is occurring, and such that a transfer to the random access memory means from the pipeline buffer means is completed before the controller processor means completes its next computation.
Claim 17
Dependent Claim
57 words
The circuitry of claim 14 wherein when said controller processor means requires a bus data transfer from the random access memory means while a local data transfer between the local processor means and random access memory means is occurring, said controller processor means waits until completion of said local data transfer before requesting said bus data transfer.
Claim 18
Dependent Claim
480 words
Circuitry for transferring path data words between a controller processor means for calculating path data and having an output means for outputting path data words and controller address signals and a local processor means for outputting local processor address signals and generating a control signal for controlling a single dimension of path motion in response to said path data words, said circuitry comprising: a single stage pipeline buffer means having an output and an input connected to the output means of said controller processor means for storing a first path data word output by said processor means while said processor means is calculating a second path data word; a bus means connected to the output of said pipeline buffer means; a random access memory means; a first gating buffer means connected between said bus means and said random access memory means for gating data therebetween in response to a first buffer gating control signal; a second gating buffer means connected between said local processor means and said random access memory means for gating data therebetween in response to a second buffer gating control signal; first switch means for gating addresses from said bus means to said random access memory means in response to a first address gating control signal; second switch means for gating addresses from said local processor means to said random access memory means in response to a second address gating control signal; and control means responsive to said controller address signals and local processor address signals for sequencing generation of said first and second buffer gating control signals and said first and second address gating control signals for controlling data transfers between said controller processor means and said random access memory means and between said local processor means and said random access memory means; wherein said control means further operates said random access memory means at a speed higher than the computational speed of said controller processor means or local processor means such that a data transfer between the local processor means and random access memory means is achieved before the controller processor means can complete computation of a path data word, and wherein said control means further operates such that a data word to be transferred from the controller processor means is stored in the pipeline buffer means while a transfer of data between the local processor means and the random access memory means is occurring, and such that a transfer to the random access memory means from the pipeline buffer means is completed before the controller processor means completes its next computation; and wherein, when said controller processor means requires a bus data transfer from the random access memory means while a local data transfer between the local processor means and random access memory means is occurring, said controller processor means waits until completion of said local data transfer before requesting said bus data transfer.
Claim 19
Dependent Claim
480 words
Circuitry for transferring path data words between a controller processor means for calculating path data and having an output means for outputting path data words and controller address signals and a local processor means for outputting local processor address signals and generating a control signal for controlling a single dimension of path motion in response to said path data words, said circuitry comprising: a single stage pipeline buffer means having an output and an input connected to the output means of said controller processor means for storing a first path data word output by said processor means while said processor means is calculating a second path data word; a bus means connected to the output of said pipeline buffer means; a random access memory means; a first gating buffer means connected between said bus means and said random access memory means for gating data therebetween in response to a first buffer gating control signal; a second gating buffer means connected between said local processor means and said random access memory means for gating data therebetween in response to a second buffer gating control signal; first switch means for gating addresses from said bus means to said random access memory means in response to a first address gating control signal; second switch means for gating addresses from said local processor means to said random access memory means in response to a second address gating control signal; and control means responsive to said controller address signals and local processor address signals for sequencing generation of said first and second buffer gating control signals and said first and second address gating control signals for controlling data transfers between said controller processor means and said random access memory means and between said local processor means and said random access memory means; wherein said control means further operates said random access memory means at a speed higher than the computational speed of said controller processor means or local processor means such that a data transfer between the local processor means and random access memory means is achieved before the controller processor means can complete computation of a path data word, and wherein said control means further operates such that a data word to be transferred from the controller processor means is stored in the pipeline buffer means while a transfer of data between the local processor means and the random access memory means is occurring, and such that a transfer to the random access memory means from the pipeline buffer means is completed before the controller processor means completes its next computation; and wherein, when said controller processor means requires a bus data transfer from the random access memory means while a local data transfer between the local processor means and random access memory means is occurring, said controller processor means waits until completion of said local data transfer before requesting said bus data transfer.
Claim 20
Dependent Claim
52 words
The circuitry of claim 16 wherein said control means includes a state machine means for occupying a first state and a second state, said first state being entered in response to receipt of said local processor address signals, the second state being entered in response to receipt of said controller address signals.
Claim 21
Dependent Claim
30 words
The circuitry of claim 17 further including a first clock means producing a succession of clock edges, and wherein said state machine runs in response to said first clock means.
Claim 22
Dependent Claim
39 words
The circuitry of claim 18 wherein said control means causes completion of data transfer between said local processor means and said random access memory means through said second gating buffer means during the period of two said clock edges.
Claim 23
Dependent Claim
73 words
The circuitry of claim 19 further including second clock means for driving said local processor means, the clock rate of said first clock means being selected to be higher than that of said second clock means and such that a data transfer is achieved between said local processor means and said random access memory means before said local processor means is capable of generating a second set of local processor address control signals.
References Cited (Backward Citations)
US4620118A
Cited
US4623971A
Cited
US4622633A
Cited
US4635206A
Cited
US4623990A
Cited
US4629955A
Cited
US4773025A
Cited
US4835710A
Cited
US4796232A
Cited
US4912633A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-10 | 1994-06-11 | 1994-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-10 | 1998-06-11 | 1998-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-10 | 2002-06-11 | 2002-12-11 | $7700.00 | Window Closed / Lapsed |