EP0378422A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Look ahead bus transfer request
Assignee: International Business Machines Corp
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Filing: 1990-01-11
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Granted: —
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Expires: 2010-01-11
Abstract
Abstract A technique for use in an I/O channel to increase bus bandwidth during DMA data transfers between main system memory and a communication link is disclosed, including a pair of buffers, a plurality of counters adapted to selectively contain a count of data increments therein, and enhanced DMA control logic for monitoring buffer data content amount, and at a predetermined time during a given transfer initiating a bus arbitration so that it is completed simultaneously with the given transfer, thereby enaoling the next data transfer to immediately commence.
Inventors
- 👤 Roger Ned Bailey
- 👤 Robert Lockwood Mansfield
- 👤 Alexander Koos Spencer
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 11:15
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
90 words
A system for performing DMA block data transfers across a non-dedicated bus between a main memory and an external device comprising: means for determining a total count of incremental data units comprising a block to be transferred; means for transferring incremental data units; means, associated with said means for transferring, for updating said total count of incremental data units to be transferred at each transfer; and means for issuing a bus request for transfer of a subsequent incremental data unit before completion of transfer of a current incremental data unit.
Claim 2
Independent Claim
90 words
A system for performing DMA block data transfers across a non-dedicated bus between a main memory and an external device comprising: means for determining a total count of incremental data units comprising a block to be transferred; means for transferring incremental data units; means, associated with said means for transferring, for updating said total count of incremental data units to be transferred at each transfer; and means for issuing a bus request for transfer of a subsequent incremental data unit before completion of transfer of a current incremental data unit.
Claim 3
Independent Claim
159 words
A system for performing a DMA transfer of a block of data across a non-dedicated bus between a main memory and an external device, said block of data comprising a plurality of incremental data units comprising: means for determining a total count of incremental data units comprising the block to be transferred; means for issuing a bus request, to request access to the bus for the transfer of one or more incremental data units; means for detecting a bus grant, means, responsive to said detecting means, for transferring one or more incremental data units on said bus when said bus grant is detected; means associated with said means for transferring, for updating at each transfer said total count of incremental data units still to be transferred; and means for issuing a bus request, to request access to the bus for the transfer of one or more subsequent incremental data units, before completion of the current incremental data unit transfer.
Claim 4
Independent Claim
159 words
A system for performing a DMA transfer of a block of data across a non-dedicated bus between a main memory and an external device, said block of data comprising a plurality of incremental data units comprising: means for determining a total count of incremental data units comprising the block to be transferred; means for issuing a bus request, to request access to the bus for the transfer of one or more incremental data units; means for detecting a bus grant, means, responsive to said detecting means, for transferring one or more incremental data units on said bus when said bus grant is detected; means associated with said means for transferring, for updating at each transfer said total count of incremental data units still to be transferred; and means for issuing a bus request, to request access to the bus for the transfer of one or more subsequent incremental data units, before completion of the current incremental data unit transfer.
Claim 5
Dependent Claim
21 words
A system as claimed in Claim 1 or Claim 2 additionally including: buffer storage for a plurality of incremental data units.
Claim 6
Dependent Claim
66 words
A system as claimed in Claim 3 wherein, during data transfer from said external device to said main memory, said means for determining comprises: in-counter means associated with said buffer storage; and receive logic for counting incremental data units as they are received, loading said incremental data units in said buffer storage, and placing a total count of incremental data units received in said in-counter means.
Claim 7
Dependent Claim
35 words
A system as claimed in claim 4, wherein: said means for transferring includes means for placing buffer storage contents on said non-dedicated bus; and said means for updating comprises means for decrementing said in-counter means.
Claim 8
Independent Claim
45 words
A system as claimed in any of Claims 3 to 5 wherein, during data transfer from said main memory to said external device, said means for determining comprises: out-counter means adapted to accept a count of data increments from a processor controlling said main memory.
Claim 9
Dependent Claim
19 words
A system as claimed in Claim 6, wherein said means for updating comprises means for decrementing said out-counter means.
Claim 10
Independent Claim
138 words
A method of performing a DMA transfer of a block of data over a shared I/O bus to a main memory from an external device said block of data comprising a plurality of data increments, comprising the steps of: a. loading data from the external device alternately into a pair of buffers, each adapted to store an integral number of said data increments; b. determining the data content of each buffer; c. initiating, whenever step b indicates a buffer is full, a DMA transfer of a fixed size increment of data from that full buffer to the I/O bus; d. issuing a bus request for each subsequent data transfer from that full buffer before transfer of the current increment of data is complete; and e. sequentially repeating steps a through d until the block of data is transferred.
Claim 11
Independent Claim
138 words
A method of performing a DMA transfer of a block of data over a shared I/O bus to a main memory from an external device said block of data comprising a plurality of data increments, comprising the steps of: a. loading data from the external device alternately into a pair of buffers, each adapted to store an integral number of said data increments; b. determining the data content of each buffer; c. initiating, whenever step b indicates a buffer is full, a DMA transfer of a fixed size increment of data from that full buffer to the I/O bus; d. issuing a bus request for each subsequent data transfer from that full buffer before transfer of the current increment of data is complete; and e. sequentially repeating steps a through d until the block of data is transferred.
Claim 12
Independent Claim
100 words
A method for transferring date in a data processing system between a main processor and an I/O channel, said data comprising a plurality of data increments and said data processing system including a shared bus connecting said main processor and said I/O channel, comprising the steps of: a. maintaining an indicator of the amount of data remaining to be transferred; b. transferring an increment of data; c. issuing a bus request for transfer of a next increment of data while step b is in progress; and d. repeating steps a through c until no more data remains to be transferred.
Claim 13
Independent Claim
100 words
A method for transferring date in a data processing system between a main processor and an I/O channel, said data comprising a plurality of data increments and said data processing system including a shared bus connecting said main processor and said I/O channel, comprising the steps of: a. maintaining an indicator of the amount of data remaining to be transferred; b. transferring an increment of data; c. issuing a bus request for transfer of a next increment of data while step b is in progress; and d. repeating steps a through c until no more data remains to be transferred.
Claim 14
Dependent Claim
122 words
DMA control apparatus for transferring a block of data between a main system processor and an external device over a shared bus, said block of data comprising a plurality of incremental data units comprising: means for indicating in real time how many incremental data units remain to be transferred; means for issuing a bus request to request access to the bus to transfer one or more incremental data units; means for detecting a bus grant, means for responsive to said detecting means, for transferring one or more incremental data units on said bus when said bus grant is detected; and means for simultaneously issuing a bus request for transfer of a subsequent incremental data unit and transferring the current incremental data unit.
Claim 15
Dependent Claim
122 words
DMA control apparatus for transferring a block of data between a main system processor and an external device over a shared bus, said block of data comprising a plurality of incremental data units comprising: means for indicating in real time how many incremental data units remain to be transferred; means for issuing a bus request to request access to the bus to transfer one or more incremental data units; means for detecting a bus grant, means for responsive to said detecting means, for transferring one or more incremental data units on said bus when said bus grant is detected; and means for simultaneously issuing a bus request for transfer of a subsequent incremental data unit and transferring the current incremental data unit.
Claim 16
Dependent Claim
40 words
DMA control apparatus as claimed in Claim 10 additionally including: means for entering a hold state if a bus grant has not been received when the current incremental data unit transfer has been completed, until a bus grant is received.
Claim 17
Independent Claim
92 words
A method of providing back to back DMA data transfers to a system processor main memory from a serial communication link comprising the steps of sequentially: (i) loading data from said link in buffer storage in DMA size increments; (ii) maintaining a current count of increments buffered; (iii)initiating bus arbitration only in response to said current count indicating a full condition in said buffer storage; (iv) placing buffered data on a bus to said main memory; (v) repeating the preceding steps until an end of data condition is detected on said link.
Claim 18
Independent Claim
92 words
A method of providing back to back DMA data transfers to a system processor main memory from a serial communication link comprising the steps of sequentially: (i) loading data from said link in buffer storage in DMA size increments; (ii) maintaining a current count of increments buffered; (iii)initiating bus arbitration only in response to said current count indicating a full condition in said buffer storage; (iv) placing buffered data on a bus to said main memory; (v) repeating the preceding steps until an end of data condition is detected on said link.
Claim 19
Dependent Claim
25 words
A method as claimed in Claim 12 including after step (iii) the additional step of: entering a hold state until a bus grant is received.
References Cited (Backward Citations)
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