Patent US2191388A successfully refreshed from Google Patents.
Patent US5299319A successfully refreshed from Google Patents.
US5299319A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High performance interlock collapsing SCISM ALU apparatus
Assignee: International Business Machines Corp
•
Filing: 1991-03-29
•
Granted: 1994-03-29
•
Expires: 2011-03-29
Abstract
Abstract Three high performance implementations for an interlock collapsing ALU are presented as alternative embodiments. The critical path delay of each embodiment provides reduction in delay. For one of the implementations the delay is shown to be an equivalent number of stages as required by a three-to-one adder assuming a commonly available bookset. The delay for the other two implementations is comparable to the three-to-one adder. In addition, trade-offs for the design complexity of implementation alternatives are set out. The embodiments achieve minimum delays without a prohibitive increase in hardware.
Inventors
- 👤 Stamatis Vassiliadis
- 👤 James E. Phillips
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:53
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/57; G06F7/575; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/38; G06F9/3836; G06F9/3853; G06F7/499; G06F7/49905; G06F7/4991
Claims Analysis
Total Claims: 45
Claim 1
Independent Claim
342 words
An apparatus for a 3-1 two's complement and unsigned number notation in an ALU that executes a pair of interlocked instructions comprising: a carry save adder (CSA) having three inputs for two unique operands and one common operand specified by said pair of interlocked instructions, said CSA having a carry output and a sum output; and a 2-1 carry-look-ahead adder (CLA) having two inputs coupled to said CSA carry and sum outputs, said CLA having an output for providing a sum equation output based upon inputs to said CLA; and a pre-CLA adder logical block coupled to operate in parallel with said CSA and having two inputs coupled to two unique inputs of said CSA and having an output coupled, along with a carry output of said CSA, to said CLA; and a post-CLA adder logical block coupled to receive said sum equation output from said CLA and a common one of the three inputs to the CSA; and wherein when a true or complement input of two unique and one common input operands specified by the pair of interlocked instructions is an input to the CSA, the CSA produces a carry and sum output; and the pre-CLA logical block is coupled to operate in parallel with the CSA and to receive the true or complement input of three unique input operands specified by the pair of interlocked instructions; and the output of the pre-CLA logical block is ORed with the carry from the CSA for providing one input to said CLA combining a carry output of said CSA and said output of said pre-CLA logical block; and the sum from the CSA is coupled to form a second input to the CLA; and the sum equation output of the CLA and the common operand input to the CSA are inputs into the post CLA logical block and logically combined for outputting an AND, OR, or EXCLUSIVE-OR signal which is then logically combined with the sum equation from the CLA to provide a conceptual sequential operation for said pair of interlocked instructions.
Claim 2
Independent Claim
342 words
An apparatus for a 3-1 two's complement and unsigned number notation in an ALU that executes a pair of interlocked instructions comprising: a carry save adder (CSA) having three inputs for two unique operands and one common operand specified by said pair of interlocked instructions, said CSA having a carry output and a sum output; and a 2-1 carry-look-ahead adder (CLA) having two inputs coupled to said CSA carry and sum outputs, said CLA having an output for providing a sum equation output based upon inputs to said CLA; and a pre-CLA adder logical block coupled to operate in parallel with said CSA and having two inputs coupled to two unique inputs of said CSA and having an output coupled, along with a carry output of said CSA, to said CLA; and a post-CLA adder logical block coupled to receive said sum equation output from said CLA and a common one of the three inputs to the CSA; and wherein when a true or complement input of two unique and one common input operands specified by the pair of interlocked instructions is an input to the CSA, the CSA produces a carry and sum output; and the pre-CLA logical block is coupled to operate in parallel with the CSA and to receive the true or complement input of three unique input operands specified by the pair of interlocked instructions; and the output of the pre-CLA logical block is ORed with the carry from the CSA for providing one input to said CLA combining a carry output of said CSA and said output of said pre-CLA logical block; and the sum from the CSA is coupled to form a second input to the CLA; and the sum equation output of the CLA and the common operand input to the CSA are inputs into the post CLA logical block and logically combined for outputting an AND, OR, or EXCLUSIVE-OR signal which is then logically combined with the sum equation from the CLA to provide a conceptual sequential operation for said pair of interlocked instructions.
Claim 3
Dependent Claim
42 words
The apparatus according to claim 1 wherein the ALU operations corresponding to the execution of an interlocked pair of instructions produce the ALU operations of: arithmetic followed by arithmetic; logical followed by arithmetic; arithmetic followed by logical; and logical followed by logical.
Claim 4
Dependent Claim
79 words
The apparatus according to claim 2 wherein the ALU operations are characterized by the form of: ______________________________________
Category 1: A + B + Γ
Arithmetic followed by
Arithmetic
Category 2: B + (A LOP Γ)
Logical followed by Arith-
metic
Category 3: B LOP (A + Γ)
Arithmetic followed by
Logical
Category 4: B LOP (A LOP Γ)
Logical followed by
Logical.
______________________________________ where A, B, and Γ correspond to the operands supplied to the said 3-1 ALU apparatus.
Claim 5
Dependent Claim
19 words
The apparatus according to claim 1 wherein the apparatus has no more logic stages than a 3-1 binary adder.
Claim 6
Dependent Claim
149 words
The apparatus according to claim 1 wherein the said pre-adder logical block has an output for a pair of instructions logical followed by arithmetic and logical followed by logical produced by L i where L i can be calculated by: L.sub.i =A.sub.i Γ.sub.i Ω.sub.AND Ω.sub.l +A.sub.i Ω.sub.OR Ω.sub.l +Γ.sub.i Ω.sub.OR Ω.sub.l +A.sub.i Γ.sub.i Ω.sub.XOR Ω.sub.l +A.sub.i Γ.sub.i Ω.sub.XOR Ω.sub.l +(A.sub.i +Γ.sub.i)Ω.sub.AND Ω.sub.l +A.sub.i Γ.sub.i Ω.sub.OR Ω.sub.l +A.sub.i Γ.sub.i Ω.sub.XOR Ω.sub.l +A.sub.i Γ.sub.1 Ω.sub.XOR Ω.sub.l L.sub.i =A.sub.i Γ.sub.i Ω.sub.AND Ω.sub.l +A.sub.i Ω.sub.OR Ω.sub.l +Γ.sub.i Ω.sub.OR Ω.sub.l +A.sub.i Γ.sub.i Ω.sub.XOR Ω.sub.l +A.sub.i Γ.sub.i Ω.sub.XOR Ω.sub.l +A.sub.i Ω.sub.AND Ω.sub.l +Γ.sub.i Ω.sub.AND Ω.sub.l +A.sub.i Γ.sub.i Ω.sub.OR Ω.sub.l +A.sub.i Γ.sub.i Ω.sub.XOR Ω.sub.l +A.sub.i Γ.sub.i Ω.sub.XOR Ω.sub.l, and wherein the assigned signal description is: ______________________________________
Signal Description
______________________________________
Ω.sub.AND
AND operands 1 and 2
Ω.sub.OR
OR operands 1 and 2
Ω.sub.XOR
COR operands 1 and 2
Ω.sub.l
Invert the result of the logical operation.
______________________________________
Claim 7
Dependent Claim
69 words
The apparatus according to claim 1 wherein said pre-adder logical block has an output of the pre-adder logical block for a pair of instructions logical followed by arithmetic and logical followed by logical produced by L i where L i can be calculated by: L.sub.i =L.sub.li (Ω.sub.OR Ω.sub.l +Ω.sub.AND Ω.sub.l)+L.sub.ri (Ω.sub.OR Ω.sub.l +Ω.sub.AND Ω.sub.l) +L.sub.li L.sub.ri (Ω.sub.AND Ω.sub.l +Ω.sub.XOR Ω.sub.l +Ω.sub.XOR Ω.sub.l)+L.sub.li L.sub.ri (Ω.sub.OR Ω.sub.l +Ω.sub.XOR Ω.sub.l +Ω.sub.XOR Ω.sub.l).sub.X.
Claim 8
Dependent Claim
82 words
The apparatus according to claim 1 wherein said pre-adder logical block has an output of the pre-adder logical block for a pair of instructions logical followed by arithmetic and logical followed by logical produced by L i where L i can be calculated by: L.sub.i =L.sub.li Ω.sub.OALASL +L.sub.ri Ω.sub.OALASL +L.sub.li L.sub.ri Ω.sub.XAAL +L .sub.li L.sub.ri Ω.sub.XOSL, where Ω.sub.OALASL =Ω.sub.OR Ω.sub.l +Ω.sub.AND Ω.sub.l Ω.sub.XAAL =Ω.sub.XOR Ω.sub.l +Ω.sub.XOR Ω.sub.l +Ω.sub.AND Ω.sub.l =Ω.sub.XOR +Ω.sub.AND Ω.sub.l Ω.sub.XOSL =Ω.sub.XOR1 Ω.sub.l +Ω.sub.XOR Ω.sub.l +Ω.sub.OR Ω.sub.l =Ω.sub.XOR +Ω.sub.OR Ω.sub.l.
Claim 9
Dependent Claim
24 words
The apparatus according to claim 7 wherein the output of the pre-adder logical block requires the same number of logic stages as a CSA.
Claim 10
Dependent Claim
35 words
The apparatus according to claim 1 wherein the inputs of the CSA of 1 are controlled to produce outputs so that they support selection between them and a parallel output of the pre-adder logic block.
Claim 11
Dependent Claim
31 words
The apparatus according to claim 9 wherein said apparatus is configured to allow the CLA to select between the output of said pre-adder logical block and the carry of the CSA.
Claim 12
Dependent Claim
43 words
The apparatus according to claim 9 wherein said input control is achieved by forcing the inputs, α i and γ i to 0 when the first instruction of an interlocked instruction pair specifies a logical operation, and the sum and carry become: ##EQU12##
Claim 13
Dependent Claim
49 words
The apparatus according to claim 9 wherein said input control is achieved by forcing the input β i to 0 when the first instruction of an interlocked instruction pair specifies a arithmetic operation, and the second instruction specifies a logical operation, and the sum and the carry become: ##EQU13##
Claim 14
Dependent Claim
48 words
The apparatus according to claim 9 wherein said input control is achieved by forcing all of the inputs to the CSA to 0 when a first instruction and a second instruction of said pair both specify logical operations and the sum and the carry become 0 as required.
Claim 15
Dependent Claim
26 words
The apparatus according to claim 1 wherein the CSA carry and the logic block output are selected as one of the two inputs to the CLA.
Claim 16
Dependent Claim
42 words
The apparatus of claim 14 wherein one of the two inputs to the CLA is selected by λ i+1 +L i , λ i+1 being the carry output of the CSA and L i being the output of the pre-adder logical block.
Claim 17
Dependent Claim
18 words
The apparatus according to claim 1 wherein an input to the CLA is the sum from the CSA.
Claim 18
Dependent Claim
20 words
The apparatus according to claim 14 wherein an other of the two inputs CLA is the sum from the CSA.
Claim 19
Dependent Claim
33 words
The apparatus according to claim 1 wherein said a post-adder logical operation when the second instruction of an interlocked pair specifies a logical operation is embedded in the sum equation of the CLA.
Claim 20
Dependent Claim
28 words
The apparatus according to claim 18 wherein the sum of the CLA incorporating the post-logical operations is computed by: Λ.sub.i =S.sub.i Ξ.sub.ADD +(S.sub.i +B.sub.i)Ξ.sub.OR +(S.sub.i B.sub.i)Ξ.sub.AND +(S.sub.i B.sub.i)Ξ.sub.XOR.
Claim 21
Dependent Claim
53 words
The apparatus according to claim 18 wherein the sum of the CLA incorporating the post-logical operations is computed by: Λ.sub.i =μ.sub.i φ.sub.i+1 +θ.sub.i φ.sub.i+1 +Ξ.sub.SOMi ; where μ.sub.i =M.sub.i Ξ.sub.GENi +M.sub.i Ξ.sub.SXMi and, θ.sub.i =H.sub.i Ξ.sub.GENi +H.sub.i Ξ.sub.SXMi ; and, Ξ.sub.GENi =Ξ.sub.ADD +Ξ.sub.OR +B.sub.i Ξ.sub.AND +B.sub.i Ξ.sub.XOR Ξ.sub.SXMi =B.sub.i Ξ.sub.XOR Ξ.sub.SOMi =B.sub.i Ξ.sub.OR.
Claim 22
Dependent Claim
59 words
The apparatus according to claim 18 wherein the sum of the CLA incorporating the post-logical operations is computed by: Λ.sub.0 =μ.sub.0 *G.sub.1.sup.tn +μ.sub.0 T.sub.2.sup.n+1 φ.sub.n+1.sup.z +θ.sub.0 G.sub.1 *.sup.n T.sub.2.sup.n+1 +θ.sub.0 G.sub.1 *.sup.n φ.sub.n+1.sup.z, where φ.sub.1 =G.sub.1 *.sup.n +T.sub.2.sup.n+1 φ.sub.n+1 and μ.sub.0 *=μ.sub.0 +Ξ.sub.SOM0, and G.sub.1.sup.tn =G.sub.1 *.sup.n +Ξ.sub.SOM0, and μ.sub.0 =M.sub.0 Ξ.sub.GEN0 +M.sub.0 Ξ.sub.SXM0 θ.sub.0 =H.sub.0 Ξ.sub.GEN0 +H.sub.0 Ξ.sub.SXM0.
Claim 23
Dependent Claim
23 words
The apparatus according to claim 1 wherein a 3-1 ALU operation can be performed with no additional delay than a 3-1 binary addition.
Claim 24
Dependent Claim
19 words
The apparatus according to claim 1 wherein the 3-1 ALU operation is performed with 5 stages characterized by: ##EQU14##
Claim 25
Dependent Claim
106 words
The apparatus according to claim 1 wherein the generation of the result for arithmetic followed by arithmetic is computed in 5 stages and characterized by: for generating A+B+Γ the signals controlling the front end of the ALU are: Ω.sub.OALASL =0 Ω.sub.XAAL =0 Ω.sub.XOSL =0 while the signals controlling the CLA are: Ξ.sub.ADD =1 Ξ.sub.OR =0 Ξ.sub.AND =0 Ξ.sub.XOR =0, and the computational stages are: ##EQU15## and wherein substituting the expressions for μ 0 , μ 0 *, θ 0 , and G 1 +18 , the output expression becomes: Λ.sub. = M.sub.0 G.sub.1 *.sup.18 +M.sub.0 T.sub.2.sup.19 φ.sub.19.sup.26 +H.sub.0 G.sub.1 *.sup.18 T .sub.2.sup.19 +H.sub.0 G.sub.1 *.sup.8 φ.sub.19.sup.26
Claim 26
Dependent Claim
26 words
The apparatus according to claim 1 wherein the generation of the result for arithmetic followed by logical is computed in 5 stages and characterized by: ##EQU16##
Claim 27
Dependent Claim
49 words
The apparatus according to claim 1 wherein the generation of the result for logical followed by arithmetic is computed in 5 stages and characterized by: ##EQU17## and where substituting μ 0 , μ 0 *, θ 0 , and G 1 +18 in the expresson for Λ 0 produces:
Claim 28
Independent Claim
148 words
An apparatus for executing a pair of interlocked instructions comprising: 3-1 addition means for addition of two's complement and unsigned numbers for executing interlocked instructions in parallel for pairs of interlocked instructions, said means including: a carry save adder (CSA) coupled to two unique and one common operand specified by a pair of interlocked instructions and a pre-adder logical block coupled for parallel operation on two unique inputs of said three inputs specified by said pair of interlocked instructions as inputs to said 3-1 addition means, a carry-look-ahead adder (CLA) for receiving the sum and a carry from the CSA, with the carry logically combined with the output of said pre-adder block; and a post-adder logical block receiving a sum equation output from said CLA and the common operand for providing the logically combined output as the result of conceptual sequential operation for said pair of interlocked instruction.
Claim 29
Independent Claim
148 words
An apparatus for executing a pair of interlocked instructions comprising: 3-1 addition means for addition of two's complement and unsigned numbers for executing interlocked instructions in parallel for pairs of interlocked instructions, said means including: a carry save adder (CSA) coupled to two unique and one common operand specified by a pair of interlocked instructions and a pre-adder logical block coupled for parallel operation on two unique inputs of said three inputs specified by said pair of interlocked instructions as inputs to said 3-1 addition means, a carry-look-ahead adder (CLA) for receiving the sum and a carry from the CSA, with the carry logically combined with the output of said pre-adder block; and a post-adder logical block receiving a sum equation output from said CLA and the common operand for providing the logically combined output as the result of conceptual sequential operation for said pair of interlocked instruction.
Claim 30
Dependent Claim
42 words
The apparatus according to claim 27 wherein the ALU operations corresponding to the execution of an interlocked pair of instructions produces the ALU operations of: arithmetic followed by arithmetic; logical followed by arithmetic; arithmetic followed by logical; and logical followed by logical.
Claim 31
Dependent Claim
79 words
The apparatus according to claim 27 wherein the ALU operations are characterized by the form of: ______________________________________
Category 1: A + B + Γ
Arithmetic followed by
Arithmetic
Category 2: B + (A LOP Γ)
Logical followed by Arith-
metic
Category 3: B LOP (A + Γ)
Arithmetic followed by
Logical
Category 4: B LOP (A LOP Γ)
Logical followed by
Logical,
______________________________________ where A, B, and Γ correspond to the operands supplied to the said 3-1 ALU apparatus.
Claim 32
Dependent Claim
18 words
The apparatus according to claim 27 wherein the apparatus has no more logic stages than a 3-1binary adder.
Claim 33
Dependent Claim
51 words
The apparatus according to claim 27 wherein the output of the pre-adder logical block for a pair of instructions logical followed by arithmetic and logical followed by logical is produced by L i wherein L i can be calculated by: L.sub.i =L.sub.li Ω.sub.OALASL +L.sub.ri Ω.sub.OALASL +L.sub.li L.sub.ri Ω.sub.XAAL +L.sub.li L.sub.ri Ω.sub.XAAL.
Claim 34
Dependent Claim
47 words
The apparatus according to claim 27 wherein one input for the CLA is set by σ.sub.i Ω.sub.4 +L.sub.i where the control signal Ω 4 =1 and L i =0 for category 1 and Ω 4 =0 and L i provides a valid input for the remaining categories.
Claim 35
Dependent Claim
27 words
The apparatus according to claim 27 wherein one input of the CLA is set by λ.sub.i =α.sub.i β.sub.i Ω.sub.1 +α.sub.i γ.sub.i Ω.sub.2 +β.sub.i γ.sub.i Ω.sub.1 +β.sub.i-1 Ω.sub.3.
Claim 36
Dependent Claim
69 words
The apparatus according to claim 33 is set by λ.sub.i =α.sub.i β.sub.i Ω.sub.1 +α.sub.i γ.sub.i Ω.sub.2 +β.sub.i γ.sub.i Ω.sub.1 +β.sub.i-1 Ω.sub.3, where Ω 1 =Ω 2 =1 and Ω 3 =0 for category 1, Ω 1 =Ω 2 0 and Ω 3 =1 for category 2, Ω 1 =Ω 3 =0 and Ω 2 =1 for category 3 and Ω 1 =Ω 2 =Ω 3 =0 for category four.
Claim 37
Dependent Claim
18 words
The apparatus according to claim 32 wherein the inputs are incorporated in the logical equations of the CLA.
Claim 38
Dependent Claim
175 words
The apparatus according to claim 35 wherein the incorporation is achieved by the following devices G.sub.i *.sup.i+1 =(σ.sub.i Ω.sub.4 +L.sub.i)λ.sub.i+1 +(σ.sub.i+1 Ω.sub.4 +L .sub.i+1)λ.sub.i+2 G.sub.i *.sup.i+1 =σ.sub.i Ω.sub.4 λ.sub.i+1 +L.sub.i λ.sub.i+1 +σ.sub.i+1 Ω.sub.4 λ.sub.i+2 +L.sub.1+1 λ.sub.i+2 ; and wherein the half sum, H i becomes: H.sub.0 =(σ.sub.i Ω.sub.4 +L.sub.i) λ.sub.i+1 H.sub.0 =(σ.sub.i Ω.sub.4 +L.sub.i)λ.sub.i+1 +(σ.sub.i Ω.sub.4 +L.sub.i)λ.sub.i+1 H.sub.0 =σ.sub.i Ω.sub.4 L.sub.i λ.sub.i+1 +σ.sub.i Ω.sub.4 λ.sub.i+1 +L.sub.i λ.sub.i+1 H.sub.0 =(σ.sub.i +Ω.sub.4)L.sub.i λ.sub.i+1 +σ.sub.i Ω.sub.4 λ.sub.i+1 L.sub.i λ.sub.i+1 H.sub.0 =σ.sub.i L.sub.i λ.sub.i+1 +Ω.sub.4 L.sub.i λ.sub.i+1 +σ.sub.i Ω.sub.4 λ.sub.i+1 L.sub.i λ.sub.i+1 ; and wherein a new carry is: φ.sub.31 =(σ.sub.31 Ω.sub.4 +L.sub.31)λ.sub.32 +τ.sub.1 φ.sub.31 =σ.sub.31 Ω.sub.4 λ.sub.32 +L.sub.31 λ.sub.32 +τ.sub.1 ; and wherein a pseudo-transmit from i to 1+1 can be generated as: T.sub.i.sup.i+1 =(σ.sub.i Ω.sub.4 +L.sub.i +λ.sub.i+1)(σ.sub.i+1 Ω.sub.4 +L.sub.i+1 +λ.sub.i+2) T.sub.i.sup.i+1 =(σ.sub.i Ω.sub.4 +L.sub.i λ.sub.i+1) (σ.sub.i+1 Ω.sub.4 +L.sub.i+1 +λ.sub.i+2) T.sub.i.sup.i+1 =(σ.sub.i Ω.sub.4 +L.sub.i +λ.sub.i+1) (σ.sub.i+1 Ω.sub.4 +L.sub.i+1 +λ.sub.i+2) T.sub.i.sup.i+1 =σ.sub.i Ω.sub.4 L.sub.i λ.sub.i+1 +σ.sub.i+1 Ω.sub.4 L.sub.i+1 λ.sub.i+2 T.sub.i.sup.i+1 =(σ.sub.i +Ω.sub.4)L.sub.i λ.sub.i+1 +(σ.sub.i+1 +Ω.sub.4)L.sub.i+1 λ.sub.i+2 T.sub.i.sup.i+1 =σ.sub.i L.sub.i λ.sub.i+1 Ω.sub.4 L.sub.i λ.sub.i+1 +σ.sub.i+1 L.sub.1+1 λ.sub.i+2 +Ω.sub.4 L.sub.i+1 λ.sub.i+2.
Claim 39
Dependent Claim
33 words
The apparatus according to claim 27 wherein said a post-adder logical operation when the second instruction of an interlocked pair specifies a logical operation is embedded in the sum equation of the CLA.
Claim 40
Dependent Claim
28 words
The apparatus according to claim 37 wherein the sum of the CLA incorporating the post-logical operations is computed by: Λ.sub.i =S.sub.i Ξ.sub.ADD +(S.sub.i +B.sub.i)Ξ.sub.OR +(S.sub.i B.sub.i)Ξ.sub.AND +(S.sub.i B.sub.i)Ξ.sub.XOR.
Claim 41
Dependent Claim
52 words
The apparatus according to claim 37 wherein the sum of the CLA incorporating the post-logical operations is computed by: Λ.sub.i =μ.sub.i φ.sub.i+1 +θ.sub.i φ.sub.i+1 +Ξ.sub.SOMi, where μ.sub.i =M.sub.i Ξ.sub.GENi +M.sub.i Ξ.sub.SXMi and, θ.sub.i =H.sub.i Ξ.sub.GENi +H.sub.i Ξ.sub.SXMi ; and, Ξ.sub.GENi =Ξ.sub.ADD +Ξ.sub.OR +B.sub.i Ξ.sub.AND +B.sub.i ΞXOR Ξ.sub.SXMi =B.sub.i Ξ.sub.XOR Ξ.sub.SOMi =B.sub.i Ξ.sub.OR.
Claim 42
Dependent Claim
58 words
The apparatus according to claim 37 wherein the sum of the CLA incorporating the post-logical operation is computed by: Λ.sub.0 =μ.sub.0 *G.sub.1.sup.+n +μ.sub.0 T.sub.2.sup.n+1 φ.sub.n+1.sup.z +θ.sub.0 G.sub.1 *.sup.n T.sub.2.sup.n+1 θ.sub.0 G.sub.1 *.sup.n φ.sub.n+1.sup.z ; wherein φ=G.sub.1 *.sup.n +T.sub.2.sup.n+1 φ.sub.n+1 and μ.sub.0 *=μ.sub.0 +Ξ.sub.SOM0, and G.sub.1.sup.+n =G.sub.1 *.sup.n +Ξ.sub.SOM0, and μ.sub.0 =M.sub.0 Ξ.sub.GEN0+M.sub.0 Ξ.sub.SXM0 θ.sub.0 =H.sub.0 Ξ.sub.GEN0 +H.sub.0 Ξ.sub.SXM0.
Claim 43
Dependent Claim
22 words
The apparatus according to claim 27 wherein a 3-1 ALU operation can be performed with no additional delay than 3-1 binary addition.
Claim 44
Dependent Claim
19 words
The apparatus according to claim 27 wherein The 3-1 ALU operation is performed with 5 stages characterized by: ##EQU18##
Claim 45
Dependent Claim
126 words
An arithmetic logic apparatus according to claim 27 wherein said 3-1 addition means executes a pair of interlocked instructions wherein an arithmetic logic unit is provided for processing instructions in a dataflow including: means for providing there input operands to said arithmetic logic unit and wherein said 3-1 addition means is provided for receiving said two unique and one common operand as three input operands and for addition of two's complement and unsigned numbers for executing the pair interlocked instructions in parallel in a single pass through said 3-1 addition means and, wherein execution of said interlocked instructions is enabled in a single pass for an interlocked instruction sequence of functions: a logical followed by arithmetic, arithmetic followed by logical; and a logical followed by logical.
References Cited (Backward Citations)
US4084254A
Cited
JPS5696328A
Cited
US4439828A
Cited
JPS58149542A
Cited
EP0118830A2
Cited
US4754412A
Cited
US4775952A
Cited
US4852040A
Cited
EP0281132A2
Cited
US4819155A
Cited
US4942548A
Cited
US4766416A
Cited
US4979141A
Cited
US5051940A
Cited
US5140545A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-28 | 1997-09-27 | 1998-03-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-28 | 2001-09-27 | 2002-03-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-28 | 2005-09-27 | 2006-03-29 | $7700.00 | Window Closed / Lapsed |