Parallel processing system apparatus

Claim 2

A processing element for use in a single instruction multiple data parallel processing system comprising a plurality of said processing elements, said element comprising: an arithmetic/logic unit (ALU) comprising electronic circuitry for performing binary logic operations on signals applied thereto; an exclusive-OR gate coupled to receive a first input signal and apply an output signal to said ALU; memory means for storing a signal, the signal stored in said memory means being outputted to said gate; and said gate providing said output signal to said ALU as the complement of said first input signal only upon a second being stored in said memory means and thereby outputted to said gate, said gate providing said output signal to said ALU as said first input signal in the absence of said second signal; so that upon storing said second signal in the respective memory means of selected ones of said processing elements of said parallel processing system and subsequently instructing all said processing elements to perform an operation on the signals applied to their respective ALUs, the selected processing elements perform the instructed operation on the complement of said first input signal while the non-selected elements perform the instructed operation on said first input signal.

Claim 3

The processing element of claim 1 wherein said memory means is responsive to a control signal to store a signal therein.

Claim 4

The processing element of claim 2 wherein said memory means is a register for storing a one bit signal.

Claim 5

The processing element of claim 1 further including multiplexing means for receiving a plurality of signals and directing one of said received signals to a multiplexing means output; said ALU including a first input for receiving said output signal from said exclusive-OR gate, a second input and an output; said multiplexing means coupled to receive a signal on said ALU output and said second signal, said multiplexing means being responsive to a multiplexing means control signal to direct either said ALU output signal or said second signal to said multiplexing means output; and said ALU second input and said memory means both coupled to receive a signal appearing on said multiplexing means output.

Claim 6

A processing element for use in a single instruction multiple data parallel processing system comprising a plurality of said processing elements, said elements comprising: an arithmetic/logic unit (ALU) having input, said ALU comprising electronic circuitry for performing binary logic operations on signals applied thereto; an exclusive-OR gate having first and second inputs and on output coupled to said ALU input; memory means for storing a signal, said memory means being coupled to said second input of said exclusive-OR gate, a signal stored in said memory means being outputted to said gate second input; and said gate providing on said gate output for application to said ALU input the signal applied to said gate first input or the complement thereof respectively according to whether a first signal is or is not stored in said memory means; so that upon storing said second signal in the respective memory means of selected ones of said processing elements of said parallel processing system and subsequently instructing all said processing elements to perform an operation on the signals applied to their respective ALUs, the selected processing elements perform the instructed operation on the complement of said first input signal while the nonselected elements perform the instructed operation on said first input signal.

Claim 7

A processing element for use in a single instruction multiple data parallel processing system comprising a plurality of said processing elements, said elements comprising: an arithmetic/logic unit (ALU) having input, said ALU comprising electronic circuitry for performing binary logic operations on signals applied thereto; an exclusive-OR gate having first and second inputs and on output coupled to said ALU input; memory means for storing a signal, said memory means being coupled to said second input of said exclusive-OR gate, a signal stored in said memory means being outputted to said gate second input; and said gate providing on said gate output for application to said ALU input the signal applied to said gate first input or the complement thereof respectively according to whether a first signal is or is not stored in said memory means; so that upon storing said second signal in the respective memory means of selected ones of said processing elements of said parallel processing system and subsequently instructing all said processing elements to perform an operation on the signals applied to their respective ALUs, the selected processing elements perform the instructed operation on the complement of said first input signal while the nonselected elements perform the instructed operation on said first input signal.

Claim 8

The processing element of claim 5 wherein said memory means is a register for holding a one bit signal.

Claim 9

The processing element of claim 5 wherein said ALU input is a first input and said memory means is a first memory means, said ALU further including second and third inputs and first and second outputs, said ALU comprising circuitry for adding binary signals applied to said ALU first and second inputs, said ALU being further coupled to receive a carry-in signal and provide a carry-out signal on said ALU third input and second output respectively; second memory means for storing a signal, said second memory means being coupled to said ALU third input, a signal stored in said second memory means being available at said ALU third input; and means for selectively storing said first signal in said first and second memory means or storing a signal on said ALU second output only in said second memory means; so that upon storing said first signal in said first and second memory means and applying second and third binary signals representative of two's complement numbers respectively to said ALU second input and said gate first input, the addition of the signals at said ALU first and second inputs by said ALU and the storage of carry-out signals in said second memory means, results in the subtraction of said third signal from said second signal.

Claim 10

The processing element of claim 7, wherein said first and second memory means respectively comprise first and second registers each for holding a one bit signal.

Claim 11

A single instruction multiple data parallel processing system comprising a plurality of processing elements, each of said elements including: an arithmetic/logic unit (ALU) comprising electronic circuitry for performing binary logic operations on signals applied thereto; an exclusive-OR gate coupled to receive a first input signal and apply an output signal to said ALU; memory means for storing a signal, the signal stored in said memory means being outputted to said gate; and said gate providing said output signal to said ALU as the complement of said first input signal only upon a second signal being stored in said memory means and thereby outputted to said gate, said gate providing said output signal to said ALU as said first input signal in the absence of said second signal; so that upon storing said second signal in the respective memory means of selected ones of said processing elements of said parallel processing system and subsequently instructing all said processing elements to perform an operation on the signals applied to their respective ALUs, the selected processing elements perform the instructed operation on the complement of said first input signal while the nonselected elements perform the instructed operation on said first input signal.

Claim 12

A single instruction multiple data parallel processing system comprising a plurality of processing elements, each of said elements including: an arithmetic/logic unit (ALU) comprising electronic circuitry for performing binary logic operations on signals applied thereto; an exclusive-OR gate coupled to receive a first input signal and apply an output signal to said ALU; memory means for storing a signal, the signal stored in said memory means being outputted to said gate; and said gate providing said output signal to said ALU as the complement of said first input signal only upon a second signal being stored in said memory means and thereby outputted to said gate, said gate providing said output signal to said ALU as said first input signal in the absence of said second signal; so that upon storing said second signal in the respective memory means of selected ones of said processing elements of said parallel processing system and subsequently instructing all said processing elements to perform an operation on the signals applied to their respective ALUs, the selected processing elements perform the instructed operation on the complement of said first input signal while the nonselected elements perform the instructed operation on said first input signal.

Claim 13

The parallel processing system of claim 9 wherein said memory means in each said element is responsive to a control signal to store a signal therein.

Claim 14

The parallel processing system of claim 9, each of said elements further including multiplexing means for receiving a plurality of signals and directing one of said received signals to a multiplexing means output; said ALU including a first input for receiving said output signal, a second input and an output; said multiplexing means coupled to receive a signal on said ALU output and said second signal, said multiplexing means being responsive to a multiplexing means control signal to direct either said ALU output signal or said second signal to said multiplexing means output; and said ALU second input and said memory means both coupled to receive a signal appearing on said multiplexing means output.

Claim 15

The parallel processing system of claim 9, wherein said memory means is a first memory means; said ALU including a first input to receive said output signal, second and third inputs and first and second outputs, said ALU comprising circuitry for adding binary signals applied to said ALU first and second inputs, receive a carry-in signal on said ALU third input and provide sum and carry-out signals on said ALU first and second outputs respectively; second memory means for storing a signal, the signal stored in said second memory means being outputted to said ALU third input; means for selectively storing either said second signal in said first and second memory means or a signal on said ALU second output in said second memory means only; and the respective ALU's of said elements in said parallel processing system each responsive to an instruction set applied thereto to perform binary logic operations, said elements in said parallel processing system coupled to simultaneously receive the same instruction set; so that upon storing said second signal in said first and second memory means in selected elements of said parallel processing system and applying said first signal and a third binary signal respectively to said gate and said ALU second input of each of said elements in said parallel processing system, and further upon applying an addition instruction to said elements in said parallel processing system, the addition of the signals at said ALU first and second inputs by said ALU and the storage of carry-out signals in said second memory means, results in the subtraction of said first signal from said third signal in said selected elements and the addition of said first and third signals in the non-selected elements.