US4942548A
Expired / Lapsed
US
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Parallel adder having removed dependencies
Assignee: International Business Machines Corp
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Filing: 1987-06-25
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Granted: 1990-07-17
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Expires: 2007-06-25
Abstract
Abstract A methodology to perform binary addition. An operand A and an operand B are presented as input and an operation is performed that respects the laws of the binary addition. The operation is performed with the use of pseudo generate signals, pseudo transmit signals, pseudo half sum signals, pseudo transmit half sum signals, a new-carry and SUM equations. The SUM equation is described for ripple or parallel configurations. All quantities can be used on single bit boundaries, or extensively for any chosen grouping of bits to accommodate chosen technology or grouping so as to facilitate the design and to increase the performance of hardware-implemented adders under the constraints of a varied technology book set. The invention also describes the implementation of a 32-bit adder that requires no more than three logic stages of delay, using a technology that allows up to 3×8 AND-OR books. Its design is achieved with the use of a SUM equation described by the general scheme of the addition and auxiliary functions that reduce the book size needed for the implementation of the sum.
Inventors
- 👤 Stamatis Vassiliadis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:08
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/506; G06F7/508
Claims Analysis
Total Claims: 53
Claim 1
Independent Claim
166 words
A method of high speed data processing through first stage, second stage and third stage logic circuits in a digital computer for adding two operands each having a predetermined length and obtaining a multibit result, the steps comprising: generating with the first stage of logic circuits based on inputs of selected portions of the two operands a plurality of pseudo signals including pseudo generate, pseudo transmit, pseudo transmit half sum, and pseudo half sum signals; generating with the second stage of logic circuits a plurality of different auxiliary signals produced from said pseudo generate, pseudo transmit, and pseudo half sum signals; generating with the second stage of logic circuits a new-carry signal described by a recursive new-carry equation based on said pseudo generate and pseudo transmit signals; and generating with the third stage of logic circuits a recursive SUM equation as a function of said pseudo signals and said auxiliary signals and said new-carry signal to produce the multibit result for further processing in the computer.
Claim 2
Independent Claim
166 words
A method of high speed data processing through first stage, second stage and third stage logic circuits in a digital computer for adding two operands each having a predetermined length and obtaining a multibit result, the steps comprising: generating with the first stage of logic circuits based on inputs of selected portions of the two operands a plurality of pseudo signals including pseudo generate, pseudo transmit, pseudo transmit half sum, and pseudo half sum signals; generating with the second stage of logic circuits a plurality of different auxiliary signals produced from said pseudo generate, pseudo transmit, and pseudo half sum signals; generating with the second stage of logic circuits a new-carry signal described by a recursive new-carry equation based on said pseudo generate and pseudo transmit signals; and generating with the third stage of logic circuits a recursive SUM equation as a function of said pseudo signals and said auxiliary signals and said new-carry signal to produce the multibit result for further processing in the computer.
Claim 3
Dependent Claim
148 words
The data processing method of adding in accordance with claim 1 wherein one of said psuedo signals comprises a psuedo generate signal from bit i to bit m, to be further delineated under the following definitions, G.sub.i =A.sub.i B.sub.i T.sub.i =A.sub.i +B.sub.i A i is the ith bith of the first of said operands and B i is the ith bit of the second of said operands, i is an integer, 0 is the most significant bit position and n is the least significant bit position of the result and bit position i of the result is less significant than bit position i-1 and more significant than bit position i+1, and such that i≦m, G*.sub.(i,m), described by the following Boolean expression: G*.sub.(i,m) =0 if i>n; and G*.sub.(i,m) =G.sub.i +G.sub.i+1 +T.sub.i+1 G.sub.i+2 +T.sub.i+1 T.sub.i+2 G.sub.i+3 + . . . +T.sub.i+1 T.sub.i+2 T.sub.i+3 . . . T.sub.m-1 G.sub.m if i≦n.
Claim 4
Dependent Claim
53 words
The data processing method of adding in accordance with claim 2 wherein one of said pseudo signals comprises a pseudo transmit signal from bit i to bit m, T.sub.(i,m), with i≦m, described by the following Boolean expression: T.sub.(i,m) =1 if i>n; and T.sub.(i,m) =T.sub.i T.sub.i+1 T.sub.i+2 . . . T.sub.m-1 T.sub.m if i≦n.
Claim 5
Dependent Claim
47 words
The method of adding in accordance with claim 3 wherein one of said pseudo signals comprises a pseudo half sum for bit i, H i , described by the following Boolean expression: H.sub.i =| if i>n H.sub.i =A.sub.i V B.sub.i if i≦n | indicates no assigned value
Claim 6
Dependent Claim
35 words
The data processing method of claim 1 for use in a ripple carry implemented adder wherein said generating steps include generating said pseudo signals and said new-carry signal for every bit position in the operands.
Claim 7
Dependent Claim
58 words
The data processing method of claim 1 for use in a parallel adder wherein said generating steps include generating said pseudo half sum and said pseudo transmit half sum signals for each bit position as well as generating said pseudo generate and said pseudo transmit and said new-carry signals for a chosen grouping of bits in the operands.
Claim 8
Dependent Claim
42 words
The data processing method of claim 1 for use in a 32 bit adder wherein said generating steps are accomplished by logic circuits formed by AND gates having no more than 3 inputs and OR gates having no more than 8 inputs.
Claim 9
Dependent Claim
253 words
In a computer, an improved high speed adder with multiple logic stages for adding two operands each having a predetermined length of 32 bits, including: first stage logic circuits; intermediate stage logic circuits receiving certain inputs generated from said first stage logic circuits in order to produce a pseudo new-carry signal and multiple auxiliary signals; final stage logic circuits receiving certain inputs generated from said first stage and said intermediate stage logic circuits including the pseudo new-carry signal and the multiple auxiliary signals; and wherein said first stage logic circuits produce a pseudo generate signal G* from bit i to bit m which constitutes at least one of the aforesaid certain inputs to said intermediate stage logic circuits to produce the pseudo new-carry signal and at least some of the multiple auxiliary signals, to be further delineated under the following definitions, G.sub.i =A.sub.i B.sub.i T.sub.i =A.sub.i +B.sub.i A i is the ith bit of the first of said operands and B i is the ith bit of the second of said operands, i is an integer, 0 is the most significant bit position and n is the least significant bit position of the result and bit position i of the result is less significant than bit position i-1 and more significant than bit position i+1, and such that i≦m, G*.sub.(i,m), described by the following Boolean expression: G*.sub.(i,m) =0 if i>n; and G*.sub.(i,m) =G.sub.i +G.sub.i+1 +T.sub.i+1 G.sub.i+2 +T.sub.i+1 T.sub.i+2 G.sub.i+3 + . . . +T.sub.i+1 T.sub.i+2 T.sub.i+3 . . . T.sub.m-1 G.sub.m if i≦n.
Claim 10
Dependent Claim
253 words
In a computer, an improved high speed adder with multiple logic stages for adding two operands each having a predetermined length of 32 bits, including: first stage logic circuits; intermediate stage logic circuits receiving certain inputs generated from said first stage logic circuits in order to produce a pseudo new-carry signal and multiple auxiliary signals; final stage logic circuits receiving certain inputs generated from said first stage and said intermediate stage logic circuits including the pseudo new-carry signal and the multiple auxiliary signals; and wherein said first stage logic circuits produce a pseudo generate signal G* from bit i to bit m which constitutes at least one of the aforesaid certain inputs to said intermediate stage logic circuits to produce the pseudo new-carry signal and at least some of the multiple auxiliary signals, to be further delineated under the following definitions, G.sub.i =A.sub.i B.sub.i T.sub.i =A.sub.i +B.sub.i A i is the ith bit of the first of said operands and B i is the ith bit of the second of said operands, i is an integer, 0 is the most significant bit position and n is the least significant bit position of the result and bit position i of the result is less significant than bit position i-1 and more significant than bit position i+1, and such that i≦m, G*.sub.(i,m), described by the following Boolean expression: G*.sub.(i,m) =0 if i>n; and G*.sub.(i,m) =G.sub.i +G.sub.i+1 +T.sub.i+1 G.sub.i+2 +T.sub.i+1 T.sub.i+2 G.sub.i+3 + . . . +T.sub.i+1 T.sub.i+2 T.sub.i+3 . . . T.sub.m-1 G.sub.m if i≦n.
Claim 11
Dependent Claim
49 words
The adder in accordance with claim 8 further comprising a pseudo transmit signal from first stage logic circuits from bit i to bit m, T.sub.(i,m), with i≦m, described by the following Boolean expression: T.sub.(i,m) =1 if i>n; and T.sub.(i,m) =T.sub.i T.sub.i+1 T.sub.i+2 . . . T.sub.m-1 T.sub.m if i≦n.
Claim 12
Dependent Claim
45 words
The adder in accordance with claim 9 further comprising a pseudo half sum from first stage logic circuits for bit i, H i , described by the following Boolean expression: H.sub.i =| if i>n H.sub.i =A.sub.i V B.sub.i if i≦n | indicates no assigned value.
Claim 13
Dependent Claim
44 words
The adder in accordance with claim 8 wherein said first, second and third stage logic circuits include AND/OR books each formed by a combination of AND gates each having no more than three inputs and OR gates each having no more than eight inputs.
Claim 14
Independent Claim
366 words
A method of high speed data processing using various logic circuits in a computer for adding two multibit binary data operands A and B which constitute digital signals in a computer in order to produce a multibit result, each operand having a predetermined length, comprising the steps of: generating with certain logic circuits in the computer a plurality of pseudo signals including a pseudo generate signal, G, from bit i to bit m, such that i≦m, G*.sub.(i,m), described by the following Boolean expression: G*.sub.(i,m) =0 if i>n; and G*.sub.(i,m) =G.sub.i +G.sub.i+1 +T.sub.i+1 G.sub.i+2 +T.sub.i+1 T.sub.i+2 G.sub.i+3 + . . . +T.sub.i+1 T.sub.i+2 T.sub.i+2 T.sub.i+3 . . . T.sub.m-1 G.sub.m if i≦n and also a psuedo transmit signal from bit i to bit m, T.sub.(i,m), with i≦m, described by the following Boolean expression: T.sub.(i,m) =1 if i>n; and T.sub.(i,m) =T.sub.i T.sub.i+1 T.sub.i+2 . . . T.sub.m-1 T.sub.m if i≦n and also a psuedo half sum for bit i, H i , described by the following Boolean expression: H.sub.i =| if i>n H.sub.i =H.sub.i V B.sub.i if i≦n and also a pseudo transmit half sum for bit, M i , described by the following Boolean expression: M.sub.i =| if H i =| M.sub.i =H.sub.i V T.sub.i+1 if H i ≠| generating a new-carry signal with additional logic circuits in the computer described by a recursive new-carry equation, with said additional logic circuits receiving inputs from the aforesaid certain logic circuits; and generating the aforesaid multibit result with further logic circuits in the computer receiving inputs from the aforesaid additional logic circuits including the new-carry signal, with said further logic circuits described by a recursive SUM equation as a function of said pseudo signals and said new-carry signal wherein G.sub.i =A.sub.i B.sub.i T.sub.i =A.sub.i +B.sub.i A i is the ith bit of the first of said operands and B i is the ith bit of the second of said operands, i is an integer, 0 is the most significant bit position and n is the least significant bit position of the result and bit position i of the result is less significant than bit position i-1 and more significant than bit position i+1, and | indicates no assigned value.
Claim 15
Independent Claim
366 words
A method of high speed data processing using various logic circuits in a computer for adding two multibit binary data operands A and B which constitute digital signals in a computer in order to produce a multibit result, each operand having a predetermined length, comprising the steps of: generating with certain logic circuits in the computer a plurality of pseudo signals including a pseudo generate signal, G, from bit i to bit m, such that i≦m, G*.sub.(i,m), described by the following Boolean expression: G*.sub.(i,m) =0 if i>n; and G*.sub.(i,m) =G.sub.i +G.sub.i+1 +T.sub.i+1 G.sub.i+2 +T.sub.i+1 T.sub.i+2 G.sub.i+3 + . . . +T.sub.i+1 T.sub.i+2 T.sub.i+2 T.sub.i+3 . . . T.sub.m-1 G.sub.m if i≦n and also a psuedo transmit signal from bit i to bit m, T.sub.(i,m), with i≦m, described by the following Boolean expression: T.sub.(i,m) =1 if i>n; and T.sub.(i,m) =T.sub.i T.sub.i+1 T.sub.i+2 . . . T.sub.m-1 T.sub.m if i≦n and also a psuedo half sum for bit i, H i , described by the following Boolean expression: H.sub.i =| if i>n H.sub.i =H.sub.i V B.sub.i if i≦n and also a pseudo transmit half sum for bit, M i , described by the following Boolean expression: M.sub.i =| if H i =| M.sub.i =H.sub.i V T.sub.i+1 if H i ≠| generating a new-carry signal with additional logic circuits in the computer described by a recursive new-carry equation, with said additional logic circuits receiving inputs from the aforesaid certain logic circuits; and generating the aforesaid multibit result with further logic circuits in the computer receiving inputs from the aforesaid additional logic circuits including the new-carry signal, with said further logic circuits described by a recursive SUM equation as a function of said pseudo signals and said new-carry signal wherein G.sub.i =A.sub.i B.sub.i T.sub.i =A.sub.i +B.sub.i A i is the ith bit of the first of said operands and B i is the ith bit of the second of said operands, i is an integer, 0 is the most significant bit position and n is the least significant bit position of the result and bit position i of the result is less significant than bit position i-1 and more significant than bit position i+1, and | indicates no assigned value.
Claim 16
Dependent Claim
48 words
The method of adding in accordance with claim 12 wherein said new-carry equation from bit i to bit m, PS.sub.(i,m), such that i≦m, is described by the following Boolean expression: PS.sub.(i,m) =Cin if i>n PS.sub.(i,m) =G*.sub.(i,m) +T.sub.(i+1,m+1) PS.sub.(m+1,z) if i≦n z being some natural number such that m<z.
Claim 17
Dependent Claim
28 words
The method of adding in accordance with claim 13 wherein said recursive SUM equation, SUM i-1 , obeys the following Boolean expression: SUM.sub.i-1 =M.sub.i-1 PS.sub.(i,m) +H.sub.i-1 PS.sub.(i,m) '.
Claim 18
Dependent Claim
37 words
The method of adding in accordance with claim 13 wherein said recursive SUM equation, SUM i-1 , obeys the following Boolean expression: SUM.sub.i-1 =M.sub.i-1 G*.sub.(i,m) +M.sub.i-1 T.sub.(i+1,m+1) PS.sub.(m+1,z) + H.sub.i-1 T.sub.(i+1,m+1) 'G*.sub.(i,m) '+ H.sub.i-1 G*.sub.(i,m) 'PS.sub.(m+1,z) '.
Claim 19
Dependent Claim
47 words
The method of adding in accordance with claim 13 wherein said recursive SUM equation, SUM i-1 , obeys the following Boolean expression: SUM.sub.i-1 =M.sub.i-1 G*.sub.(i,m) +M.sub.i-1 T.sub.(i+1,m+1) G*.sub.(m+1,z) + M.sub.i-1 T.sub.(i+1,z+1) PS.sub.(z+1,k) + H.sub.i-1 T.sub.(i+1, m+1)'G*.sub.(i,m) '+ H.sub.i-1 G*.sub.(i,m) 'T.sub.(m+2,z+1) +'G*.sub.(m+1,z) '+ H.sub.i-1 G*.sub.(i,m) 'G*.sub.(m+1,z) 'PS.sub.(z+1,k) '.
Claim 20
Dependent Claim
33 words
The method of adding in accordance with claim 13 wherein recurrences of new-carry equations are removed until said new-carry equations equal the carry into said addition, resulting in a plurality of SUM expressions.
Claim 21
Dependent Claim
281 words
A high speed data processing system in a computer having a three stage logic adder with various logic circuits for adding two operands each having a predetermined length of 32 bits including first circuit means in the adder for creating a psuedo generate signal, G', from bit i to bit m, such that i≦m, G*.sub.(i,m), described by the following Boolean expression: G*.sub.(i,m) =0 if i>n; and G*.sub.(i,m) =G.sub.i +G.sub.i+1 +T.sub.i+1 G.sub.i+2 +T.sub.i+1 T.sub.i+2 G.sub.i+3 + . . . +T.sub.i+1 T.sub.i+2 T.sub.i+3 . . . T.sub.m-1 G.sub.m if i≦n second circuit means in the adder for creating a psuedo transmit signal from bit i to bit m, T.sub.(i,m), with i≦m, described by the following Boolean expression: T.sub.(i,m) =1 if i>n; and T.sub.(i,m) =T.sub.i T.sub.i+1 T.sub.i+2 . . . T.sub.m-1 T.sub.m if i≦n third circuit means in the adder for creating a psuedo half sum for bit i, H i , described by the following Boolean expression: H.sub.i =| if i>n H.sub.i =A.sub.i B.sub.i if i≦n fourth circuit means in the adder for creating a psuedo transmit half sum for bit i, M i , described by the following Boolean expression: M.sub.i =| if H.sub.i =| M.sub.i =H.sub.i T.sub.i+1 if H.sub.i ≠| wherein G.sub.i =A.sub.i B.sub.i T.sub.i =A.sub.i +B.sub.i A i is the ith bit of the first of the operands and B i is the ith bit of the second of the operands, i is an integer, 0 is the most significant bit position and n is the least significant bit position of the result and bit position i of the result is less significant than bit position i-1 and more significant than bit position i+1, and | indicates no assigned value.
Claim 22
Dependent Claim
281 words
A high speed data processing system in a computer having a three stage logic adder with various logic circuits for adding two operands each having a predetermined length of 32 bits including first circuit means in the adder for creating a psuedo generate signal, G', from bit i to bit m, such that i≦m, G*.sub.(i,m), described by the following Boolean expression: G*.sub.(i,m) =0 if i>n; and G*.sub.(i,m) =G.sub.i +G.sub.i+1 +T.sub.i+1 G.sub.i+2 +T.sub.i+1 T.sub.i+2 G.sub.i+3 + . . . +T.sub.i+1 T.sub.i+2 T.sub.i+3 . . . T.sub.m-1 G.sub.m if i≦n second circuit means in the adder for creating a psuedo transmit signal from bit i to bit m, T.sub.(i,m), with i≦m, described by the following Boolean expression: T.sub.(i,m) =1 if i>n; and T.sub.(i,m) =T.sub.i T.sub.i+1 T.sub.i+2 . . . T.sub.m-1 T.sub.m if i≦n third circuit means in the adder for creating a psuedo half sum for bit i, H i , described by the following Boolean expression: H.sub.i =| if i>n H.sub.i =A.sub.i B.sub.i if i≦n fourth circuit means in the adder for creating a psuedo transmit half sum for bit i, M i , described by the following Boolean expression: M.sub.i =| if H.sub.i =| M.sub.i =H.sub.i T.sub.i+1 if H.sub.i ≠| wherein G.sub.i =A.sub.i B.sub.i T.sub.i =A.sub.i +B.sub.i A i is the ith bit of the first of the operands and B i is the ith bit of the second of the operands, i is an integer, 0 is the most significant bit position and n is the least significant bit position of the result and bit position i of the result is less significant than bit position i-1 and more significant than bit position i+1, and | indicates no assigned value.
Claim 23
Dependent Claim
24 words
The adder in accordance with claim 18 comprising AND-OR books not greater than a size of three-way AND gate and eight-way OR gate configurations.
Claim 24
Dependent Claim
50 words
The adder in accordance with claim 18 further comprising fifth circuit means creating a new-carry from bit i to bit m, PS.sub.(i,m), such that i≦m, is described by the following Boolean expression: PS.sub.(i,m) =Cin if i>n PS.sub.(i,m) =G*.sub.(i,m) +T.sub.(i+1,m+1) PS.sub.(m+1,z) if i≦n z being some natural number such that m<z.
Claim 25
Dependent Claim
26 words
The adder in accordance with claim 20 wherein a recursive SUM equation, SUM i-1 , obeys the following Boolean expression: SUM.sub.i-1 =M.sub.i-1 PS.sub.(i,m) +H.sub.i-1 PS.sub.(i,m) '.
Claim 26
Dependent Claim
35 words
The adder in accordance with claim 20 wherein a recursive SUM equation, SUM i-1 , obeys the following Boolean expression: SUM.sub.i-1 =M.sub.i-1 G*.sub.(i,m) +M.sub.i-1 T.sub.(i+1,m+1) PS.sub.(m+1,z) + H.sub.i-1 T.sub.(i+1,m+1) 'G*.sub.(i,m) '+ H.sub.i-1 G*.sub.(i,m) 'PS.sub.(m+1,z) '.
Claim 27
Dependent Claim
45 words
The adder in accordance with claim 20 wherein a recursive SUM equation, SUM i-1 , obeys the following Boolean expression: SUM.sub.i-1 =M.sub.i-1 G*.sub.(i,m) +M.sub.i-1 T.sub.(i+1,m+1) G*.sub.(m+1,z) + M.sub.i-1 T.sub.(i+1,z+1) PS.sub.(z+1,k) + H.sub.i-1 T.sub.(i+1,m+1) 'G*.sub.(i,m) '+ H.sub.i-1 G*.sub.(i,m) 'T.sub.(m+2,z+1) 'G*.sub.(m+1,z) '+ H.sub.1-1 G*.sub.(i,m) 'G*.sub.(m+1,z) 'PS.sub.(z+1,k) '.
Claim 28
Dependent Claim
74 words
The adder in accordance with claim 21 comprising a critical SUM equation implementing the following Boolean expression for i=0 : SUM.sub.(i) =M.sub.(i) G*.sub.(i+1,9) +Q.sub.(i,5) R.sub.(6,15) + Q.sub.(i,5) T.sub.(6,12) W.sub.(13,21) + Q.sub.(i,5) T.sub.(6,22) PS.sub.(22,29) + H.sub.(i) T.sub.(i+2,10) 'G*.sub.(i+1,9) '+ X.sub.(i,9) Z.sub.(11,15) + X.sub.(i,9) G*.sub.(10,15) 'L.sub.(16,22) + X.sub.(i,9)Y(10,21) PS.sub.(22,29) ' with: Q.sub.(i,5) =M.sub.(i) T.sub.(i+2,5) R.sub.(6,15) =T.sub.(6,10) G*.sub.(10,15) W.sub.(13,21) =T.sub.(13,16) G*.sub.(16,21) X.sub.(i,9) =H.sub.(i) G*.sub.(i+1,9) ' Z.sub.(11,15) =T.sub.(11,16) 'G*.sub.(10,15) ' L.sub.(16,22) =G*.sub.(16,21) 'T.sub.(17,22) ' Y.sub.(10,21) =G*.sub.(10,15) 'G*.sub.(16,21) '.
Claim 29
Dependent Claim
73 words
The adder in accordance with claim 22 comprising a critical SUM equation implementing the following Boolean expression for i=0: SUM.sub.(i) =M.sub.(i) G*.sub.(i+1,9) +Q.sub.(i,5) R.sub.(6,15) + Q.sub.(i,5) T.sub.(6,12) W.sub.(13,21) + Q.sub.(i,5) T.sub.(6,22) PS.sub.(22,29) + H.sub.(i) T.sub.(i+2,10) 'G*.sub.(i+1,9) '+ X.sub.(i,9) Z.sub.(11,15) + X.sub.(i,9) G*.sub.(10,15) 'L.sub.(16,22) + X.sub.(i,9)Y(10,21) PS.sub.(22,29) ' with: Q.sub.(i,5) =M.sub.(i) T.sub.(i+2,5) R.sub.(6,15) =T.sub.(6,10) G*.sub.(10,15) W.sub.(13,21) =T.sub.(13,16) G*.sub.(16,21) X.sub.(i,9) =H.sub.(i) G*.sub.(i+1,9) ' Z.sub.(11,15) =T.sub.(11,16) 'G*.sub.(10,15) ' L.sub.(16,22) =G*.sub.(16,21) 'T.sub.(17,22) ' Y.sub.(10,21) =G*.sub.(10,15) 'G*.sub.(16,21) '.
Claim 30
Dependent Claim
73 words
The adder in accordance with claim 23 comprising a critical SUM equation implementing the following Boolean expression for i=0: SUM.sub.(i) =M.sub.(i) G*.sub.(i+1,9) +Q.sub.(i,5) R.sub.(6,15) + Q.sub.(i,5) T.sub.(6,12) W.sub.(13,21) + Q.sub.(i,5) T.sub.(6,22) PS.sub.(22,29) + H.sub.(i) T.sub.(i+2,10) 'G*.sub.(i+1,9) '+ X.sub.(i,9) Z.sub.(11,15) + X.sub.(i,9) G*.sub.(10,15) 'L.sub.(16,22) + X.sub.(i,9)Y(10,21) PS.sub.(22,29) ' with: Q.sub.(i,5) =M.sub.(i) T(.sub.i+2,5) R.sub.(6,15) =T.sub.(6,10) G*.sub.(10,15) W.sub.(13,21) =T.sub.(13,16) G*.sub.(16,21) X.sub.(i,9) =H.sub.(i) G*.sub.(i+1,9) ' Z.sub.(11,15) =T.sub.(11,16) 'G*.sub.(10,15) ' L.sub.(16,22) =G*.sub.(16,21) 'T.sub.(17,22) ' Y.sub.(10,21) =G*.sub.(10,15) 'G*.sub.(16,21) '.
Claim 31
Dependent Claim
34 words
The adder in accordance with claim 24 comprising a critical SUM equation for any of the bits 1-31 properly extending from said i=0 critical SUM equation and in accordance with said recursive SUM equations.
Claim 32
Dependent Claim
34 words
The adder in accordance with claim 25 comprising a critical SUM equation for any of the bits 1-31 properly extending from said i=0 critical SUM equation and in accordance with said recursive SUM equations.
Claim 33
Dependent Claim
34 words
The adder in accordance with claim 26 comprising a critical SUM equation for any of the bits 1-31 properly extending from said i=0 critical SUM equation and in accordance with said recursive SUM equations.
Claim 34
Dependent Claim
34 words
The adder in accordance with claim 27 wherein pseudo quantities and their complements obey the following Boolean expression for i=0: G*.sub.(i+1,9) =G*.sub.(i+1,3) +T.sub.(i+2,4) G*.sub.(4,6) +T.sub.(i+2,4) T.sub.(5,7) G*.sub.(7,9) G*.sub.(i+1,9) '=(G*.sub.(i+1,3) +T.sub.(i+2,4) G*.sub.(4,6) +T.sub.(i+2,4) T(.sub.5,7) G*.sub.7,9))'.
Claim 35
Dependent Claim
36 words
The adder in accordance with claim 28 wherein pseudo quantities and their complements obey the following Boolean expression for i=0: G*.sub.(i+1,9) =G*.sub.(i+1,3) +T.sub.(i+2,4) G*.sub.(4,6) + T.sub.(i+2,4) T.sub.(5,7) G*.sub.(7,9) G*.sub.(i+1,9) '=(G*.sub.(i+1,3) +T.sub.(i+2,4) G*.sub.(4,6) + T.sub.(i+2,4) T.sub.(5,7) G*.sub.(7,9))'.
Claim 36
Dependent Claim
36 words
The adder in accordance with claim 29 wherein pseudo quantities and their complements obey the following Boolean expression for i=0: G*.sub.(i+1,9) =G*.sub.(i+1,3) +T.sub.(i+2,4) G*.sub.(4,6) + T.sub.(i+2,4) T.sub.(5,7) G*.sub.(7,9) G*.sub.(i+1,9) '=(G*.sub.(i+1,3) +T.sub.(i+2,4) G*.sub.(4,6) + T.sub.(i+2,4) T.sub.(5,7) G*.sub.(7,9))'.
Claim 37
Dependent Claim
75 words
The adder in accordance with claim 30 wherein auxiliary functions are defined by the following Boolean expressions: Q.sub.(i,5) =H.sub.(i) 'T.sub.(i+1) T.sub.(i+2,5) +H.sub.(i) T.sub.(i+1) 'T.sub.(i+2,5) R.sub.(6,15) =T.sub.(6,10) G*.sub.(10,15) =T.sub.(6,9) T.sub.(10) G*.sub.(10,12) + T.sub.(6,9) T.sub.(10,13) G*.sub.(13,15) W.sub.(13,21) =T.sub.(13,16) G*.sub.(16,21) =T.sub.(13,16) G*.sub.(16,18) + T.sub.(13,16) G*.sub.(17,19) G*.sub.(19,21) X.sub.(i,9) =(H.sub.(i) '+G*.sub.(i+1,i+3) + T.sub.(i+2,i+4) G*.sub.(i+4,i+6) + T.sub.(i+2,i+4) T.sub.(i+5,i+7) G*.sub.(i+7,9))' Z.sub.(11,15) =(T.sub.(11,13) T.sub.(14,16) +G*.sub.(10,12) + T.sub.(11,13) G*.sub.(13,15))' L.sub.(16,22) =(G*.sub.(16,18) +T.sub.(17,19) G*.sub.(19,21) + T.sub.(17,20) T.sub.(21,22))' Y.sub.(10,21) =(G*.sub.(10,12) +T.sub.(11,13) G*.sub.(13,15) + G*.sub.(16,18) +T.sub.(17,19) G*.sub.(19,21))'.
Claim 38
Dependent Claim
75 words
The adder in accordance with claim 31 wherein auxiliary functions are defined by the following Boolean expressions: Q.sub.(i,5) =H.sub.(i) 'T.sub.(i+1) T.sub.(i+2,5) +H.sub.(i) T.sub.(i+1) 'T.sub.(i+2,5) R.sub.(6,15) =T.sub.(6,10) G*.sub.(10,15) =T.sub.(6,9) T.sub.(10) G*.sub.(10,12) + T.sub.(6,9) T.sub.(10,13) G*.sub.(13,15) W.sub.(13,21) =T.sub.(13,16) G*.sub.(16,21) =T.sub.(13,16) G*.sub.(16,18) + T.sub.(13,16) G*.sub.(17,19) G*.sub.(19,21) X.sub.(i,9) =(H.sub.(i) '+G*.sub.(i+1,i+3) + T.sub.(i+2,i+4) G*.sub.(i+4,i+6) + T.sub.(i+2,i+4) T.sub.(i+5,i+7) G*.sub.(i+7,9))' Z.sub.(11,15) =(T.sub.(11,13) T.sub.(14,16) +G*.sub.(10,12) + T.sub.(11,13) G*.sub.(13,15))' L.sub.(16,22) =(G*.sub.(16,18) +T.sub.(17,19) G*.sub.(19,21) + T.sub.(17,20) T.sub.(21,22))' Y.sub.(10,21) =(G*.sub.(10,12) +T.sub.(11,13) G*.sub.(13,15) + G*.sub.(16,18) +T.sub.(17,19) G*.sub.(19,21))'.
Claim 39
Dependent Claim
75 words
The adder in accordance with claim 32 wherein auxiliary functions are defined by the following Boolean expressions: Q.sub.(i,5) =H.sub.(i) 'T.sub.(i+1) T.sub.(i+2,5) +H.sub.(i) T.sub.(i+1) 'T.sub.(i+2,5) R.sub.(6,15) =T.sub.(6,10) G*.sub.(10,15) =T.sub.(6,9) T.sub.(10) G*.sub.(10,12) + T.sub.(6,9) T.sub.(10,13) G*.sub.(13,15) W.sub.(13,21) =T.sub.(13,16) G*.sub.(16,21) =T.sub.(13,16) G*.sub.(16,18) + T.sub.(13,16) G*.sub.(17,19) G*.sub.(19,21) X.sub.(i,9) =(H.sub.(i) '+G*.sub.(i+1,i+3) + T.sub.(i+2,i+4) G*.sub.(i+4,i+6) + T.sub.(i+2,i+4) T.sub.(i+5,i+7) G*.sub.(i+7,9))' Z.sub.(11,15) =(T.sub.(11,13) T.sub.(14,16) +G*.sub.(10,12) + T.sub.(11,13) G*.sub.(13,15))' L.sub.(16,22) =(G*.sub.(16,18) +T.sub.(17,19) G*.sub.(19,21) + T.sub.(17,20) T.sub.(21,22))' Y.sub.(10,21) =(G*.sub.(10,12) +T.sub.(11,13) G*.sub.(13,15) + G*.sub.(16,18) +T.sub.(17,19) G*.sub.(19,21))'.
Claim 40
Dependent Claim
48 words
The adder in accordance with claim 33 wherein a new-carry equation for bit 22 and its complement are defined by the following Boolean expressions: PS.sub.(22,29) =G*.sub.(22,24) +T.sub.(23,25) G*.sub.(25,27) + T.sub.(23,25) T.sub.(26,28) G*.sub.(28,29) + T.sub.(23,26) T.sub.(27,30) PS.sub.(30) PS.sub.(22,29) '=(G*.sub.(22,24) +T.sub.(23,25) G*.sub.(25,27) + T.sub.(23,25) T.sub.(26,28) G*.sub.(28,29) + T.sub.(23,26) T.sub.(27,30) PS.sub.(30))'.
Claim 41
Dependent Claim
48 words
The adder in accordance with claim 34 wherein a new-carry equation for bit 22 and its complement are defined by the following Boolean expressions: PS.sub.(22,29) =G*.sub.(22,24) +T.sub.(23,25) G*.sub.(25,27) + T.sub.(23,25) T.sub.(26,28) G*.sub.(28,29) + T.sub.(23,26) T.sub.(27,30) PS.sub.(30) PS.sub.(22,29) '=(G*.sub.(22,24) +T.sub.(23,25) G*.sub.(25,27) + T.sub.(23,25) T.sub.(26,28) G*.sub.(28,29) + T.sub.(23,26) T.sub.(27,30) PS.sub.(30))'.
Claim 42
Dependent Claim
48 words
The adder in accordance with claim 35 wherein a new-carry equation for bit 22 and its complement are defined by the following Boolean expressions: PS.sub.(22,29) =G*.sub.(22,24) +T.sub.(23,25) G*.sub.(25,27) + T.sub.(23,25) T.sub.(26,28) G*.sub.(28,29) + T.sub.(23,26) T.sub.(27,30) PS.sub.(30) PS.sub.(22,29) '=(G*.sub.(22,24) +T.sub.(23,25) G*.sub.(25,27) + T.sub.(23,25) T.sub.(26,28) G*.sub.(28,29) + T.sub.(23,26) T.sub.(27,30) PS.sub.(30))'.
Claim 43
Dependent Claim
52 words
The adder in accordance with claim 36 wherein a pseudo transmit signal for bit groups from 1 to 3 is defined by the following Boolean expressions: T.sub.(i,i+3) =(A.sub.(i) +B.sub.(i)) (A.sub.(i+1) +B.sub.(i+1)) (A.sub.(i+2) + B.sub.(i+2)) (A.sub.(i+3) +B.sub.(i+3)) T.sub.(i) =A.sub.(i) +B.sub.(i) T.sub.(i,i+1) =(A.sub.(i) +B.sub.(i)) (A.sub.(i+1) +B.sub.(i+1)) T.sub.(i,i+2) =(A.sub.(i) +B.sub.(i)) (A.sub.(i+1) +B.sub.(i+1)) (A.sub.(i+2) + B.sub.(i+2)).
Claim 44
Dependent Claim
52 words
The adder in accordance with claim 37 wherein a pseudo transmit signal for bit groups from 1 to 3 is defined by the following Boolean expressions: T.sub.(i,i+3) =(A.sub.(i) +B.sub.(i)) (A.sub.(i+1) +B.sub.(i+1)) (A.sub.(i+2) + B.sub.(i+2)) (A.sub.(i+3) +B.sub.(i+3)) T.sub.(i) =A.sub.(i) +B.sub.(i) T.sub.(i,i+1) =(A.sub.(i) +B.sub.(i)) (A.sub.(i+1) +B.sub.(i+1)) T.sub.(i,i+2) =(A.sub.(i) +B.sub.(i)) (A.sub.(i+1) +B.sub.(i+1)) (A.sub.(i+2) + B.sub.(i+2)).
Claim 45
Dependent Claim
52 words
The adder in accordance with claim 38 wherein a pseudo transmit signal for bit groups from 1 to 3 is defined by the following Boolean expressions: T.sub.(i,i+3) =(A.sub.(i) +B.sub.(i)) (A.sub.(i+1) +B.sub.(i+1) (A.sub.(i+2) + B.sub.(i+2)) (A.sub.(i+3) +B.sub.(i+3)) T.sub.(i) =A.sub.(i) +B.sub.(i) T.sub.(i,i+1) =(A.sub.(i) +B.sub.(i)) (A.sub.(i+1) +B.sub.(i+1)) T.sub.(i,i+2) =(A.sub.(i) +B.sub.(i)) (A.sub.(i+1) +B.sub.(i+1)) (A.sub.(i+2) + B.sub.(i+2)).
Claim 46
Dependent Claim
45 words
The adder in accordance with claim 39 wherein a pseudo generate signal for bit groups 1 to 2 is defined by the following Boolean expressions: G*.sub.(i) =A.sub.(i) B.sub.(i) G*.sub.(i,i+1) =A.sub.(i) B.sub.(i) +A.sub.(i+1) B.sub.(i+1) G*.sub.(i,i+2) =A.sub.(i) B.sub.(i) +A.sub.(i+1) B.sub.(i+1) + A.sub.(i+1) A.sub.(i+2) B.sub.(i+2) +B.sub.(i+1) A.sub.(i+2) B.sub.(i+2).
Claim 47
Dependent Claim
45 words
The adder in accordance with claim 40 wherein a pseudo generate signal for bit groups 1 to 2 is defined by the following Boolean expressions: G*.sub.(i) =A.sub.(i) B.sub.(i) G*.sub.(i,i+1) =A.sub.(i) B.sub.(i) +A.sub.(i+1) B.sub.(i+1) G*.sub.(i,i+2) =A.sub.(i) B.sub.(i) +A.sub.(i+1) B.sub.(i+1) + A.sub.(i+1) A.sub.(i+2) B.sub.(i+2) +B.sub.(i+1) A.sub.(i+2) B.sub.(i+2).
Claim 48
Dependent Claim
45 words
The adder in accordance with claim 41 wherein a pseudo generate signal for bit groups 1 to 2 is defined by the following Boolean expressions: G*.sub.(i) =A.sub.(i) B.sub.(i) G*.sub.(i,i+1) =A.sub.(i) B.sub.(i) +A.sub.(i+1) B.sub.(i+1) G*.sub.(i,i+2) =A.sub.(i) B.sub.(i) +A.sub.(i+1) B.sub.(i+1) + A.sub.(i+1) A.sub.(i+2) B.sub.(i+2) +B.sub.(i+1) A.sub.(i+2) B.sub.(i+2).
Claim 49
Dependent Claim
42 words
The adder in accordance with claim 42 wherein a new-carry equation for bit 30 and its complement are defined by the following Boolean expressions: PS.sub.(30) =A.sub.(30) B.sub.(30) +A.sub.(31) B.sub.(31) +A.sub.(31) Cin+ B.sub.(31) Cin PS.sub.(30) '=(A.sub.(30) B.sub.(30) +A.sub.(31) B.sub.(31) +A.sub.(31) Cin+ B.sub.(31) Cin)'.
Claim 50
Dependent Claim
42 words
The adder in accordance with claim 43 wherein a new-carry equation for bit 30 and its complement are defined by the following Boolean expressions: PS.sub.(30) =A.sub.(30) B.sub.(30) +A.sub.(31) B.sub.(31) +A.sub.(31) Cin+ B.sub.(31) Cin PS.sub.(30) '=(A.sub.(30) B.sub.(30) +A.sub.(31) B.sub.(31) +A.sub.(31) Cin+ B.sub.(31) Cin)'.
Claim 51
Dependent Claim
42 words
The adder in accordance with claim 44 wherein a new-carry equation for bit 30 and its complement are defined by the following Boolean expressions: PS.sub.(30) =A.sub.(30) B.sub.(30) +A.sub.(31) B.sub.(31) +A.sub.(31) Cin+ B.sub.(31) Cin PS.sub.(30) '=(A.sub.(30) B.sub.(30) +A.sub.(31) B.sub.(31) +A.sub.(31) Cin+ B.sub.(31) Cin)'.
Claim 52
Dependent Claim
105 words
In a computer, an improved high speed adder with multiple logic stages for adding two operands each having a predetermined length of 32 bits, including first stage logic circuits, intermediate stage logic circuits receiving certain inputs from said first stage logic circuits, and final stage logic circuits receiving certain inputs from said intermediate stage logic circuits, wherein said first stage, intermediate and final stage logic circuits comprise AND-OR books not greater than a size of 3×8 where 3 refers to the maximum number of inputs for each AND gate and 8 refers to the maximum number of AND gates providing inputs to the OR gate.
Claim 53
Dependent Claim
105 words
In a computer, an improved high speed adder with multiple logic stages for adding two operands each having a predetermined length of 32 bits, including first stage logic circuits, intermediate stage logic circuits receiving certain inputs from said first stage logic circuits, and final stage logic circuits receiving certain inputs from said intermediate stage logic circuits, wherein said first stage, intermediate and final stage logic circuits comprise AND-OR books not greater than a size of 3×8 where 3 refers to the maximum number of inputs for each AND gate and 8 refers to the maximum number of AND gates providing inputs to the OR gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-16 | 1994-01-15 | 1994-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-16 | 1998-01-15 | 1998-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-16 | 2002-01-15 | 2002-07-17 | $7700.00 | Window Closed / Lapsed |