US4348736A
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Programmable logic array adder
Assignee: International Business Machines Corp
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Filing: 1980-07-22
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Granted: 1982-09-07
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Expires: 2000-07-22
Abstract
Abstract This specification discloses a multi digit binary adder embodied in programmable logic arrays (PLAs). The particular programmable logic array used here has a separate two-bit decoder for receiving each like order pairs of digits A i , B i of two n digit binary numbers A 0 , A 1 . . . A n-1 and B 0 , B 1 . . . B n-1 plus a carry C in . The decoders generate an output signal called a minterm on a different line for each of the four possible combinations A i ·B i , A i ·B i , A i ·B i and A i ·B i of the true and complement of each pair. The minterms from the decoders are fed to an array called the product term generator or AND array which generates product terms f.sub.p =f.sub.0 (A.sub.0,B.sub.0)·f.sub.1 (A 1 ,B 1 )· . . . ·f n-1 (A n-1 ,B n-1 )·f n (C in ) The product terms are fed to a second array called a sums of product terms generator or OR array that sums product terms f p . A series of latches is last in the sequence of logic elements making up the PLA. These latches each perform an Exclusive-OR function to generate a sum bit S i that is an Exclusive-OR of two functions supplied by the OR array to the inputs of the latches to generate a sum S 0 , S 1 . . . S n-1 plus a carry C out for the adder at the output of the PLA. The adder is optimized for a PLA with latches that perform an Exclusive-OR function and is more efficient than known adders embodied in PLAs, in which the output latches perform an AND function.
Inventors
- 👤 Arnold Weinberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:40
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/5057
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
185 words
In a carry look ahead adder for the addition of two multi digit numbers A 0 , A i . . . A n-1 and B 0 , B 1 . . . B n-1 (0 to n-1 high-to-low order) and an input carry digit C in to generate a multi digit binary sum S 0 , S 1 . . . S n-1 and a carry out digit C out using programmable logic arrays each such programmable logic array including a plurality of multi bit input decoders feeding signals to a product term generating array which in turn feeds signals to a sum of product term generating array that supplies signals to Exclusive-OR circuits providing an Exclusive-OR function of two inputs, the improvement comprising: means feeding like order digits A i , B i of the two multi digit numbers to the same multi bit input decoder; and circuit means in the product term and sum of product term generating arrays to generate a sum digit S i as the output of one of the Exclusive-OR circuits in accordance with the following formula: ##EQU19##
Claim 2
Dependent Claim
185 words
In a carry look ahead adder for the addition of two multi digit numbers A 0 , A i . . . A n-1 and B 0 , B 1 . . . B n-1 (0 to n-1 high-to-low order) and an input carry digit C in to generate a multi digit binary sum S 0 , S 1 . . . S n-1 and a carry out digit C out using programmable logic arrays each such programmable logic array including a plurality of multi bit input decoders feeding signals to a product term generating array which in turn feeds signals to a sum of product term generating array that supplies signals to Exclusive-OR circuits providing an Exclusive-OR function of two inputs, the improvement comprising: means feeding like order digits A i , B i of the two multi digit numbers to the same multi bit input decoder; and circuit means in the product term and sum of product term generating arrays to generate a sum digit S i as the output of one of the Exclusive-OR circuits in accordance with the following formula: ##EQU19##
Claim 3
Dependent Claim
185 words
In a carry look ahead adder for the addition of two multi digit numbers A 0 , A 1 . . . A n-1 and B 0 , B 1 . . . B n-1 (0 to n-1 high-to-low order) and an input carry digit C in to generate a multi digit binary sum S 0 , S 1 . . . S n-1 and a carry out digit C out using programmable logic arrays each such programmable logic array including a plurality of multi bit input decoders feeding signals to a product term generating array which in turn feeds signals to a sum of product term generating array that supplies signals to Exclusive-OR circuits providing an Exclusive-OR function of two inputs, the improvement comprising, means feeding like order digits A i , B i of the two multi digit numbers to the same multi bit input decoder; and circuit means in the product term and sum of product term generating arrays to generate a sum digit S i as the output of one of the Exclusive-OR circuits in accordance with the following formula: ##EQU20##
Claim 4
Dependent Claim
185 words
In a carry look ahead adder for the addition of two multi digit numbers A 0 , A 1 . . . A n-1 and B 0 , B 1 . . . B n-1 (0 to n-1 high-to-low order) and an input carry digit C in to generate a multi digit binary sum S 0 , S 1 . . . S n-1 and a carry out digit C out using programmable logic arrays each such programmable logic array including a plurality of multi bit input decoders feeding signals to a product term generating array which in turn feeds signals to a sum of product term generating array that supplies signals to Exclusive-OR circuits providing an Exclusive-OR function of two inputs, the improvement comprising, means feeding like order digits A i , B i of the two multi digit numbers to the same multi bit input decoder; and circuit means in the product term and sum of product term generating arrays to generate a sum digit S i as the output of one of the Exclusive-OR circuits in accordance with the following formula: ##EQU20##
Claim 5
Dependent Claim
187 words
In a carry look ahead adder for the addition of two multi digit numbers A 0 , A 1 . . . A n-1 and B 0 , B 1 . . . B n-1 (0 to n-1 high-to-low order) and an input carry digit C in to generate a multi digit binary sum S 0 , S 1 , . . . B n-1 and a carry out digit C out using programmable logic arrays each such programmable logic array including a plurality of two bit input decoders feeding signals to a product term generating array which in turn feeds signals to a sum of product term generating array that supplies signals to Exclusive-OR circuits providing an Exclusive-OR function of two inputs, the improvement comprising: means feeding like order digits A i B i of the two multi digit numbers to the same two bit input decoder; and circuit means in the product term and sum of product term generating arrays to generate an intermediate order sum digit S i as the output of one of the Exclusive-OR circuits in accordance with the following formula: ##EQU21##
Claim 6
Dependent Claim
187 words
In a carry look ahead adder for the addition of two multi digit numbers A 0 , A 1 . . . A n-1 and B 0 , B 1 . . . B n-1 (0 to n-1 high-to-low order) and an input carry digit C in to generate a multi digit binary sum S 0 , S 1 , . . . B n-1 and a carry out digit C out using programmable logic arrays each such programmable logic array including a plurality of two bit input decoders feeding signals to a product term generating array which in turn feeds signals to a sum of product term generating array that supplies signals to Exclusive-OR circuits providing an Exclusive-OR function of two inputs, the improvement comprising: means feeding like order digits A i B i of the two multi digit numbers to the same two bit input decoder; and circuit means in the product term and sum of product term generating arrays to generate an intermediate order sum digit S i as the output of one of the Exclusive-OR circuits in accordance with the following formula: ##EQU21##
Claim 7
Dependent Claim
187 words
In a carry look ahead adder for the addition of two multi digit numbers A 0 , A 1 . . . A n-1 and B 0 , B 1 . . . B n-1 (0 to n-1 high-to-low order) and an input carry digit C in to generate a multi digit binary sum S 0 , S 1 . . . S n-1 and a carry out digit C out using programmable logic arrays each such programmable logic array including a plurality of two bit input decoders feeding signals to a product term generating array which in turn feeds signals to a sum of product term generating array that supplies signals to Exclusive-OR circuits providing an Exclusive-OR function of two inputs, the improvement comprising: means feeding like order digits A i , B i of the two multi digit numbers to the same two bit input decoder; and circuit means in the product term and sum of product term generating arrays to generate any intermediate order sum digit S i as the output of one of the Exclusive-OR circuits in accordance with the following formula: ##EQU22##
Claim 8
Dependent Claim
187 words
In a carry look ahead adder for the addition of two multi digit numbers A 0 , A 1 . . . A n-1 and B 0 , B 1 . . . B n-1 (0 to n-1 high-to-low order) and an input carry digit C in to generate a multi digit binary sum S 0 , S 1 . . . S n-1 and a carry out digit C out using programmable logic arrays each such programmable logic array including a plurality of two bit input decoders feeding signals to a product term generating array which in turn feeds signals to a sum of product term generating array that supplies signals to Exclusive-OR circuits providing an Exclusive-OR function of two inputs, the improvement comprising: means feeding like order digits A i , B i of the two multi digit numbers to the same two bit input decoder; and circuit means in the product term and sum of product term generating arrays to generate any intermediate order sum digit S i as the output of one of the Exclusive-OR circuits in accordance with the following formula: ##EQU22##
Claim 9
Dependent Claim
30 words
The adder of claim 3 or 4 including circuit means in the product term and sum of product term arrays to generate any intermediate carry C i according to: ##EQU23##
Claim 10
Dependent Claim
30 words
The adder of claim 3 or 4 including circuit means in the product term and sum of product term arrays to generate any intermediate carry C i according to: ##EQU24##
Claim 11
Dependent Claim
33 words
The adder of claim 3 or 4 including circuit means in the product term and sum of product term arrays and exclusive OR circuits generating an output carry C out equal to: ##EQU25##
Claim 12
Dependent Claim
33 words
The adder of claim 3 or 4 including circuit means in the product term and sum of product term arrays and exclusive OR circuits generating an output carry C out equal to: ##EQU26##
Claim 13
Dependent Claim
40 words
The adder of claim 3 or 4 including circuit means in the product term and sum of product term arrays and exclusive OR circuits to generate succeeding sum bits S j from any intermediate carry C j+1 as follows: ##EQU27##
Claim 14
Dependent Claim
40 words
The adder of claim 3 or 4 including circuit means in the product term and sum of product term arrays and exclusive OR circuits to generate succeeding sum bits S j from any intermediate carry C j+l as follows: ##EQU28##
Claim 15
Dependent Claim
61 words
The adder of claim 3 or 4 including circuit means in the product term and sum of product term arrays for generating any particular intermediate string of sum bits S n-l-k , . . . S n-l-1 having a length set by formula: l=K.sup.2 +K-3 where l=the number of low-order bits preceding said string, K=the number of bits in said string.
Claim 16
Dependent Claim
41 words
The carry look ahead adder of claim 3 or 4 including circuit means in the product term and sum of product term arrays and exclusive OR circuits generating the low-order carry and sum digits in accordance with the following formulas: ##EQU29##
Claim 17
Dependent Claim
41 words
The carry look ahead adder of claim 3 or 4 including circuit means in the product term and sum of product term arrays and exclusive OR circuits generating the low-order carry and sum digits in accordance with the following formulas: ##EQU30##
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-09-06 | 1986-03-08 | 1986-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-09-06 | 1990-03-08 | 1990-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-09-06 | 1994-03-08 | 1994-09-07 | $7700.00 | Window Closed / Lapsed |