Patent US2145842A successfully refreshed from Google Patents.
US4157590A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable logic array adder
Assignee: International Business Machines Corp
•
Filing: 1978-01-03
•
Granted: 1979-06-05
•
Expires: 1998-01-03
Abstract
Abstract This specification discloses a multi digit binary adder embodied in programmable logic arrays (PLAs). The particular programmable logic array used here has a separate two bit decoder for receiving each like order pairs of digits A i , B i of two n digit binary numbers A 0 , A 1 ....A n-1 and B 0 , B 1 ....B n-1 plus a carry C in . The decoders generate an output signal called a min term on a different line for each of the four possible combinations A i B i , A i B i , A i B i and A i B i of the true and complement of each pair. The min terms from the decoders are fed to an array called the product term generator or AND array which generates product terms f.sub.p =f.sub.0 (A.sub.0,B.sub.0) f.sub.1 (A.sub.1,B.sub.1)....f.sub.n-1 (A n-1 , B n-1 ) f n (C in ) The product terms are fed to a second array called a sum of product term generator or OR array that sums product terms f p . A series of latches is last in the sequence of logic elements making up the PLA. These latches each perform an AND function to generate a sum bit S i that is an AND of two functions supplied by the OR array to the inputs of the latches to generate a sum S 0 , S 1 ....S n-1 plus a carry C out for the adder at the output of the PLA. The adder is optimized for a PLA with latches that perform an AND function.
Inventors
- 👤 Donald G. Grice
- 👤 David F. Johnson
- 👤 Arnold Weinberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:10
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/5057
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
267 words
In a carry look ahead adder for the addition of two multi digit numbers A 0 , A 1 . . . A n-1 and B 0 , B 1 . . . B n-1 with an input carry digit C in to generate a multi digit binary sum S 0 , S 1 , S 2 . . . S n-1 and a carry out digit C out using programmable logic arrays each with a plurality of two bit input decoders feeding signals to a product term generating array which in turn feeds signals to a sum of product term generating array that supplies signals to AND circuits providing an AND function of two inputs, the improvement comprising: means feeding like order digits A i , B i of the two multi digit numbers to the same two bit input decoder; and circuit means in the product term and sum of product term generating arrays providing inputs to one of said AND circuits to generate a sum digit S i as the output of said one of the AND circuits in accordance with; ______________________________________
##STR1##
##STR2##
and alternatively:
##STR3##
##STR4##
where: High to low order is from 0 to n-1 G i =A i ·B i P i =A i ·B i H i =A i V B i [H i ] H i =A i V B i =A i V B i =A V B i i=a bit position of the sum j=a bit position of any order lower than i C i+j+1 =the carry out from bit position i+j+1 into bit position i+j
Claim 2
Dependent Claim
267 words
In a carry look ahead adder for the addition of two multi digit numbers A 0 , A 1 . . . A n-1 and B 0 , B 1 . . . B n-1 with an input carry digit C in to generate a multi digit binary sum S 0 , S 1 , S 2 . . . S n-1 and a carry out digit C out using programmable logic arrays each with a plurality of two bit input decoders feeding signals to a product term generating array which in turn feeds signals to a sum of product term generating array that supplies signals to AND circuits providing an AND function of two inputs, the improvement comprising: means feeding like order digits A i , B i of the two multi digit numbers to the same two bit input decoder; and circuit means in the product term and sum of product term generating arrays providing inputs to one of said AND circuits to generate a sum digit S i as the output of said one of the AND circuits in accordance with; ______________________________________
##STR1##
##STR2##
and alternatively:
##STR3##
##STR4##
where: High to low order is from 0 to n-1 G i =A i ·B i P i =A i ·B i H i =A i V B i [H i ] H i =A i V B i =A i V B i =A V B i i=a bit position of the sum j=a bit position of any order lower than i C i+j+1 =the carry out from bit position i+j+1 into bit position i+j
Claim 3
Dependent Claim
19 words
The carry lookahead adder of claim 1 wherein the low order sum digits are generated in accordance with: ##EQU12##
Claim 4
Dependent Claim
36 words
The carry look ahead adder of claim 2 wherein the lowest order bit of the low order sum digits is generated in accordance with: S.sub.n-1 =H.sub.n-1 ·C.sub.in +H.sub.n-1 ·C.sub.in and alternatively: S.sub.n-1 =H.sub.n-1 ·C.sub.in +H.sub.n-1 ·C.sub.in.
Claim 5
Dependent Claim
14 words
The adder of claim 1 where any intermediate carry is generated according to: ##EQU13##
Claim 6
Dependent Claim
29 words
The adder of claim 4 where the output carry is generated according to: ##EQU14## where q=the highest order bit position for which an input carry C q+1 is available.
Claim 7
Dependent Claim
31 words
The adder of claim 4 where the complement of the output carry is generated according to: ##EQU15## where q=the highest order bit position for which an input C q+1 is available.
Claim 8
Dependent Claim
42 words
The adder of claim 4 where the length T of an intermediate string of product terms is T=K 2 +5+2L where L is the number of lower order bits preceding said string and K is the number of bits in said string.
Claim 9
Dependent Claim
90 words
In a carry-look ahead adder implemented in a programmed logic array of the type having input bit decoding means, an AND array, an OR array, and AND gates at the inputs to output latches, the improvement comprising: a first portion of said AND array implementing carry-look ahead terms which are part of the carry-look ahead calculation for at least two sum bit positions; another portion of said AND array implementing not carry-look ahead terms which are part of the not carry-look ahead calculation for at least two sum bit positions.
Claim 10
Dependent Claim
90 words
In a carry-look ahead adder implemented in a programmed logic array of the type having input bit decoding means, an AND array, an OR array, and AND gates at the inputs to output latches, the improvement comprising: a first portion of said AND array implementing carry-look ahead terms which are part of the carry-look ahead calculation for at least two sum bit positions; another portion of said AND array implementing not carry-look ahead terms which are part of the not carry-look ahead calculation for at least two sum bit positions.
Claim 11
Dependent Claim
68 words
In a carry-look ahead adder implemented in a programmed logic array of the type having input bit decoding means, an AND array, an OR array, and AND gates at the inputs to output latches, the improvement comprising: a portion of said AND array implementing product terms which are shared by the high order sum bit of a string of sum bits and the carry out from said string.
Claim 12
Dependent Claim
68 words
In a carry-look ahead adder implemented in a programmed logic array of the type having input bit decoding means, an AND array, an OR array, and AND gates at the inputs to output latches, the improvement comprising: a portion of said AND array implementing product terms which are shared by the high order sum bit of a string of sum bits and the carry out from said string.
Claim 13
Dependent Claim
68 words
In a carry-look ahead adder implemented in a programmed logic array of the type having input bit decoding means, an AND array, an OR array, and AND gates at the inputs to output latches, the improvement comprising: a portion of said AND array implementing product terms which are shared by two high order sum bits of a string, said two high order sum bits being of opposite polarity.
Claim 14
Dependent Claim
68 words
In a carry-look ahead adder implemented in a programmed logic array of the type having input bit decoding means, an AND array, an OR array, and AND gates at the inputs to output latches, the improvement comprising: a portion of said AND array implementing product terms which are shared by two high order sum bits of a string, said two high order sum bits being of opposite polarity.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-06-04 | 1982-12-04 | 1983-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-06-04 | 1986-12-04 | 1987-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-06-04 | 1990-12-04 | 1991-06-05 | $7700.00 | Window Closed / Lapsed |